Senior Digital ASIC Design Engineer Synthesis (m/f/d)

Advantest; Böblingen; On-site; EUR 90,000 - 120,000; Full time

Job summary

Advantest Europe GmbH in Böblingen sucht einen erfahrenen Digital ASIC Design Engineer (Synthesis). Sie arbeiten in einem globalen, hochqualifizierten Ingenieurteam und übernehmen End-to-End-Verantwortung von der ersten Konzeptualisierung bis zum Silizium.

Sie arbeiten eng mit Systemarchitekten und Design-Ingenieuren zusammen, erstellen Constraint-Skripte, analysieren Pfad- und Leistungsanforderungen und unterstützen Floorplanning und physikalisches Design.

Qualifications

• Universitätsabschluss, Diplom oder BS in EE.
• Hintergrund in digitalem Design (SOC) und im ASIC-Entwicklungszyklus.
• Erfahrung in RTL-Codierung (Verilog/SystemVerilog).
• Erfahrung mit Standard-Simulationstools für digitale Designs.
• Grundkenntnisse in UNIX/Linux sowie Programmierkenntnisse.
• Technische Kommunikation, Teamarbeit und Problemlösungsfähigkeiten.
• Englische Sprachkenntnisse.

Responsibilities

• Architekturentwicklung für CMOS-Designs.
• Design und RTL-Codierung digitaler/fulls-custom Module.
• Verifikation auf Modul- und Chip-Ebene inkl. Testplanung/-fällen.
• Dokumentation implementierter Funktionalität.
• Generierung von Constraints und Synthese von IP-Blöcken und Chip-Hauptstrukture.
• Analyse von Timing und Leistungsaufnahme.
• Unterstützung bei Floorplanning und physischem Design.
• Enge Zusammenarbeit mit Design-Partnern.

Skills

Digital design

ASIC design

RTL coding

Verilog/SystemVerilog

Unix/Linux

English

Teamwork

Problem solving

Education

University degree in EE

Tools

Simulation tools

Job description

Aufgabe

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing. You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership. In this role, you will collaborate closely with system architects and design engineers. You will generate constraints for synthesis of IP blocks and the chip top level integration. You will analyze critical paths for robust designs, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

• Architecture development for CMOS designs
• Design and RTL coding of digital and full-custom modules
• Verification on module and chip level including test plan/cases generation.
• Documentation of implemented functionality
• Constraint generation and synthesis of IP blocks and the chip top level
• Analysis of timing and power consumption
• Support for floor-planning and physical design
• Close collaboration with design partners

Senior Digital ASIC Design Engineer Synthesis (m/f/d)

Advantest Europe GmbH

Böblingen

Kennziffer: 8197

Aufgabe

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing. You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership. In this role, you will collaborate closely with system architects and design engineers. You will generate constraints for synthesis of IP blocks and the chip top level integration. You will analyze critical paths for robust designs, keep power consumption under control, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

• Architecture development for CMOS designs
• Design and RTL coding of digital and full-custom modules
• Verification on module and chip level including test plan/cases generation.
• Documentation of implemented functionality
• Constraint generation and synthesis of IP blocks and the chip top level
• Analysis of timing and power consumption
• Support for floor-planning and physical design
• Close collaboration with design partners

Qualifikation

• University degree, Diploma or BS EE
• Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle
• Experience in Register Transfer Level (RTL) coding (Verilog and System Verilog)
• Experience with standard simulation tools for digital designs
• Basic knowledge about UNIX* or Linux* environment and using programming languages
• Technical communication, team work and problem solving skills
• English language skills