Senior Digital ASIC Design Engineer (m/f/d)

Advantest; Böblingen; On-site; EUR 70,000 - 95,000; Full time

Job summary

Advantest Europe GmbH in Böblingen is seeking a Digital ASIC Design Engineer (m/f/d) to join a global, highly skilled engineering team. You will develop digital modules and subsystems from concept to silicon, taking end-to-end ownership of complex ASIC designs used in advanced semiconductor testers.

The role requires RTL coding (Verilog), experience with digital design methodologies, and collaboration with system architects, software, and product teams.

Qualifications

• University degree in EE or related field.
• Experience with RTL coding (Verilog) for ASIC design.
• Experience with digital design for SOC/ASIC development.
• Familiarity with UNIX/Linux environments.
• Strong communication and teamwork; English skills.

Responsibilities

• Gather requirements for CMOS IP architecture development.
• Design and RTL coding of digital modules.
• Verify at module and chip level with test plans.
• Document functionality.
• Assist floorplanning and physical design.
• Collaborate with cross-functional teams.

Skills

RTL coding

Digital design

Verilog

ASIC development

Unix/Linux

English communication

Education

Electrical Engineering degree

Tools

Verilog simulators

Unix/Linux tools

Job description

Advantest Europe GmbH

Böblingen

Digital ASIC Design Engineer (m/f/d)

Aufgabe

Join a global, highly skilled engineering team at the heart of Advantest's cutting edge IC test solutions. As a Digital ASIC Design Engineer, you will help create the key technologies that enable the next generation of semiconductor testing. You will work on complex mixed signal ASICs used in Advantest's industry leading testers, taking digital modules and subsystems from first concept all the way to silicon in the final system, giving you true end to end ownership. In this role, you will collaborate closely with system architects, software engineers, product marketing, and other engineering disciplines. You will translate requirements into robust designs, solve challenging technical problems, and deliver high quality results on schedule and at scale.

Job Duties & Responsibilities

• Requirements gathering and elicitation for IP Architecture development for CMOS IP designs
• Design and RTL coding of digital and full-custom modules
• Verification on module and chip level including test plan/cases generation
• Documentation of implemented functionality
• Support for floor-planning and physical design
• Collaboration with other functions

Qualifikation

• University degree, Diploma or BS EE
• Background in digital design (SOC), Application Specific Integrated Circuit (ASIC) design methodologies and silicon development cycle
• Experience in Register Transfer Level (RTL) coding (Verilog)
• Experience with standard simulation tools for digital designs
• Basic knowledge about UNIX* or Linux* environment and using programming languages
• Technical communication, team work and problem solving skills
• English language skills