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Senior Design Verification Engineer

Nityo Infotech

Hamburg

Vor Ort

EUR 60.000 - 80.000

Vollzeit

Vor 30+ Tagen

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Zusammenfassung

An innovative firm is seeking a Senior Technical Recruiter with expertise in technical recruiting and a solid background in testbench design and verification. This role involves working with advanced EDA tools and methodologies to ensure high-quality verification processes for digital IP and SoCs. The ideal candidate will possess strong communication skills and a proactive attitude, contributing to a dynamic team environment. Join a forward-thinking company that values technical excellence and offers opportunities for professional growth in the exciting field of IT services and consulting.

Qualifikationen

  • Experience in testbench design and verification sign-off using UVM methodology.
  • Proven skills in using EDA tools from Cadence and Synopsys.

Aufgaben

  • Design and develop testbenches for IP/Subsystem/SoCs using UVM methodology.
  • Conduct verification sign-off and develop test plans.

Kenntnisse

Testbench design and development
Verification sign-off
UVM methodology
Communication skills
Fluency in English

Tools

Cadence tools (Xcelium, Simvision, Verisium, vManager, Jasper)
Synopsys tools (VCS, Verdi)

Jobbeschreibung

Senior Technical Recruiter at Nityo Infotech | Expertise in Technical Recruiting

Location: Hamburg, Germany

Employment Type: B2B Contract

Profile
  • Proven experience in testbench design and development using UVM methodology for IP/Subsystem/SoCs.
  • Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis.
  • Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, vManager, Jasper) and/or Synopsys (VCS, Verdi).
  • Understanding of software development for embedded CPUs, and experience in developing and debugging software.
  • Basic experience in execution of Gate Level Netlist simulation with back-annotated timing.
  • Basic experience on writing System Verilog assertions.
  • Basic understanding of Formal flow/methodologies.
  • Ability to question and identify weaknesses in specifications, tool environments, etc.
  • Pro-active attitude with proven experience in digital IP & SoC verification and good communication skills.
  • Fluency in English language.
Seniority Level

Mid-Senior level

Job Function

Design, Information Technology, and Engineering

Industries

IT Services and IT Consulting, Software Development, and IT System Design Services

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