Research Associate “Layout Engineer” (m/f/d)

Barkhausen Institut; Dresden; Vor Ort; EUR 52.000 - 73.000; Vollzeit

Benefits dieser Stelle

Training und Chip-Tape-Out-Erfahrung

Offenes, kreatives Team

Flexible Arbeitszeiten

Unterstützung bei der Ankunft in Dresd

Zusammenfassung

Das Barkhausen-Institut sucht eine/n Research Associate – Layout Engineer in Dresden. Sie arbeiten an Layout-Design und Floorplanning digitaler ICs, einschließlich Gedächtniss-Makros, und unterstützen die gesamte physische Verifikation sowie Timing-Analysen.

Voraussetzungen sind ein MSc/Diplom oder Doktor in Electrical/Computer Engineering sowie gute Englischkenntnisse. Es erwartet Sie ein offenes, kreatives Team mit flexiblen Arbeitszeiten und dem Ziel, Open-Source-PDKs und fortschrittliche

Qualifikationen

• MSc/Diplom oder PhD in Electrical-/Computer Engineering von renommierten Universitäten.
• Gute Kommunikations- und Schreibfähigkeiten in Englisch.
• Erfahrung mit EDA-Tools für IC-Design (z. B. Cadence, Synopsys).
• Integrative, kooperative Persönlichkeit mit ausgeprägten Kommunikations- und Sozialkompetenzen.

Aufgaben

• Layout-Design und Floorplanning digitaler IC-Designs inklusive Memory-Makros und benutzerdefinierter Logik.
• Vollständiges Layout und physische Verifikation (DRC, LVS, ERC).
• Timing-Analyse und Power-Optimierung.
• Unterstützung RTL-to-GDSII-Flows für fortschrittliche Prozessknoten (z. B. 12nm FDSOI) und Open-Source-PDKs (z. B. IHP 130nm).
• Kundenspezifisches Layout für analoge Blöcke (Training wird angeboten).

Kenntnisse

Layout design

Floorplanning

Timing analysis

Power optimization

RTL-to-GDSII

Ausbildung

MSc/Diploma or PhD in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Jobbeschreibung

The Barkhausen Institut performs research on the latest hardware, software and communication technologies and demonstrates their application in tomorrow's society. Our goal is to build a flexible and trustworthy IoT platform based on reliable electronics and secure communication methods.

Research Associate “Layout Engineer” (m/f/d)

The position will initially be filled for a period of 2 years and will be remunerated in line with TV-L E-13. The position aims at supporting further academic qualification (e.g. PhD).

Your Responsibilities Will Include

• Layout design and floorplanning of digital IC designs including memory macros and custom logic implementations
• Full layout and physical verification (DRC, LVS, ERC)
• Timing analysis and power optimization
• Support RTL-to-GDSII design flows for:
  • advanced process nodes, e.g. 12nm FDSOI
  • open-source PDKs, e.g. IHP 130nm
• Custom layout for analog blocks (training will be provided)

We expect the following

• MSc/Diploma or PhD degree in areas related to our research focus (Electrical/Computer Engineering) from renowned universities
• Good communication and writing skills in English
• An integrative and cooperative personality with excellent communication and social skills
• Prior experience with EDA tools for IC design, e.g. from Cadence or Synopsys

What We Provide

• Training and exposure to chip tape-outs in advanced process nodes
• Experience in full development cycles of custom IC
• An open and creative team
• Agile working hours and workflows
• Cross-disciplinary projects
• Work on future technologies
• Flat hierarchies for your ideas and flexible teams
• Our remuneration is based on the collective agreement for the federal states. If you meet all the professional requirements (diploma/master's degree or doctorate), this position is classified as TV-L E 13. Depending on your professional experience, the basic monthly salary ranges between €4,629 and €6,580. We will be happy to provide more details during the interview.

This position is ideal for gaining serious exposure to IC development cycles and it can be a key enabler for ambitions to work in Custom/Digital IC industry. If you have passion for new technologies and the desire to develop the connected world of tomorrow with us, we are looking for you.

Life and science are compatible at our institute. We offer a range of recognised family-friendly measures, such as part-time work, mobile working and flexible working hours that take family needs into account. We also offer support for arriving in Dresden (all formalities, apartment etc.).

Application Procedure

• Applications from women are particularly welcome.
• Barkhausen Institut strives for gender and diversity equality. We welcome applications from all backgrounds. Severely disabled persons are given preference in the event of equal suitability.

The data submitted by you in the course of the application procedure will be processed by the Barkhausen Institut (BI). BI shall use the data for the purposes of the application procedure. No data shall be passed on to third parties.

Skills zu dieser Stellenanzeige: IoT, BI, Barkhausen Institut, physical verification, power optimization, Computer Engineering, IC design, designer, layout design und layout engineer