Principal Verification Engineer

microTECH Global Ltd; München; Vor Ort; EUR 70.000 - 110.000; Vollzeit

Zusammenfassung

An innovative company is seeking a Principal Digital Verification Engineer to lead design verification efforts in the automotive and smart devices sectors. This role involves collaborating with cross-functional teams to ensure compliance with ISO functional safety standards while leveraging extensive experience in hardware description languages and CADENCE tools. The ideal candidate will possess over 8 years of experience in design verification and have a strong background in functional safety processes. Join a forward-thinking organization that is at the forefront of technology and make a significant impact on cutting-edge solutions.

Qualifikationen

• 8+ years of experience in design verification with leadership in verification tasks.
• Proficient in hardware description languages and functional safety processes.

Aufgaben

• Collaborate with design and verification teams to ensure compliance with specifications.
• Develop verification processes adhering to functional safety standards.

Kenntnisse

Design Verification

Functional Safety

Verilog

VHDL

SystemC

SystemVerilog

SpecmanE

UVM

Ausbildung

Degree in Electrical Engineering

Degree in Computer Science

Tools

CADENCE Tools

Xcelium

VManager

Specman/e

JasperGold

Jobbeschreibung

Job Title : Principal Digital Verification Engineer

Job Type : Permanent

Start : ASAP

Our client-

We are working with a “solution SoC” company with rich experience in different markets leading innovations with customers around the world.

In the fields of “automotive”, “data centre & networking”, and “smart devices”, functionality and performance are becoming increasingly sophisticated, they design and develop their products based on common concepts, including subsystem configuration and bus architecture, and deliver SoCs that meet their scalability needs and enable the optimal function and performance for each application.

Responsibilities-

• You work with engineers of the Design Team and Verification Team to carry out the Design Verification (SpecmanE, UVM)
• You proceed with development (design and verification) in compliance with ISO (Functional Safety)
• You work with safety manager, project manager and development team on functional safety work products.

Profile -

• You have a degree in electrical engineering, computer science or similar.
• You have solid experience (8+ years) in the area of design verification.
• You have led the verification team performing verification tasks according to the functional safety processes.
• You are not only proficient in hardware description languages (Verilog, VHDL, SystemC, SystemVerilog), but bring extensive experience across the entire SoC design flow.
• You have experience in functional safety and in the use of relevant tools and methods.
• You have experience with CADENCE tools for Functional Verification like Xcelium, VManager, Specman / e and JasperGold.