Precision Senior Analog IC Design Engineer

IC Resources; Berlin; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

IC Resources in Berlin seeks a seasoned Senior Analog IC Designer to join a leading technology company active in silicon photonics and high-performance semiconductor chips. You will design DC op-amps, biasing blocks, and fast analog circuits in CMOS/BiCMOS, build chip hierarchies in Cadence, and develop interfacing analog IP with I2C/SPI control to meet stringent system requirements.

The role requires 5+ years of IC design experience with Cadence Virtuoso and EIC design flows, plus a strong

Qualifikationen

• Master’s degree in Electrical Engineering or a related field.
• 5+ years of IC design experience in CMOS/BiCMOS.
• Proven Cadence Virtuoso experience and EIC design workflow knowledge.

Aufgaben

• Design DC op-amps, biasing circuits, digital gates, and high-speed analog blocks.
• Build chip-level hierarchies within Cadence.
• Interface analog ICs with I2C/SPI control via IP blocks.
• Collaborate with photonics team to meet system-level specs.

Kenntnisse

Analog IC design

Cadence Virtuoso

Bandgap references

Control loops

Ausbildung

Master’s degree in Electrical Engineering

Tools

Cadence Virtuoso

EIC design tools

DFM workflows

Jobbeschreibung

A leading and well funded technology company specialising in silicon photonics-based interconnect solutions that develops innovative semiconductor chips for next-generation data centers, utilising in-house Photonic Integrated Circuit (PIC) and Electronic Integrated Circuit (EIC) design capabilities is looking for a seasoned Analog IC Designer with a strong background in auxiliary circuits to control, signal, monitor, or protect a primary power circuits. They collaborate with large-volume CMOS foundries as manufacturing partners to deliver state-of-the-art products.

As Senior Analog IC Design Engineer you will be able to work independently from day one within a dynamic and international team. In this role, you will contribute to the design and development of cutting‑edge electro‑optical transceiver chips, working closely with a team of experts to achieve groundbreaking advancements in the field.

Responsibilities

• Design DC operational amplifiers, biasing circuits, digital gates, analog multiplexers, and high-speed analog circuits in CMOS (or BiCMOS) technologies
• Build chip‑level hierarchies within a Cadence environment
• Develop auxiliary circuits to interface analog ICs with I2C or SPI digital control interfaces using IP blocks
• Apply advanced layout techniques to optimize current density and minimize parasitics, layout device matching
• Design IC pad frames for various technologies, including die bonding, flip‑chip, micro‑bumps, and micro‑Cu‑pillar, and create corresponding netlists
• Develop temperature‑independent biasing blocks using bandgap references
• Define and adhere to design methodologies and environments to ensure high‑quality outcomes
• Collaborate closely with the photonic design team to co‑design electrical and optical components, meeting stringent system‑level performance requirements across technology corners

Qualifications

• Master’s degree in Electrical Engineering or a related field
• 5+ years of industry experience in integrated circuit design in CMOS or BiCMOS in Bandgap, Current Bias, Current references, Operational Amplifiers, Voltage Regulators, Comparators, Control loops like Automatic Gain Control.
• Extensive experience with EIC design tools, particularly the Cadence Virtuoso and proven experience in developing actual products.
• In‑depth knowledge of chip‑level electronic design flows for Design for Manufacturability (DFM) with a strong commitment to product quality and reliability
• Proactive problem‑solving skills and the ability to work effectively in a team‑oriented, dynamic environment

If you are passionate about innovation and eager to make a significant impact in the field of silicon photonics and integrated circuit design, we would love to hear from you. Please contact Ane @ IC Resoucres with your CV.