PMU Digital Design Verification Intern (m/f/d)

Apple; Baden-Baden; Presencial; EUR 11 000 - 18 000; Tempo parcial

Resumo da oferta

Apple in Nabern (near Stuttgart) invites a motivated Design Verification Intern to contribute to pre‑silicon validation for mixed‑signal designs, collaborating with Digital and Analog Design engineers.

You will develop verification plans, build test benches, generate tests, run simulations, and improve coverage using SystemVerilog/UVM, Python, and scripting, while learning in a fast‑paced hardware environment.

Qualificações

• Bachelor's in EE or related field is required.
• Excellent communication and interpersonal skills, combined with the ability to collaborate.
• Ability to work well on a team, take ownership and motivate self and others.
• Fluent English skills (written and verbal).
• Good knowledge of SystemVerilog and UVM.
• Experience with Python, Perl or TCL.
• Good knowledge of Object Oriented Programming.
• Available for 6 months or more.

Responsabilidades

• Develop verification plans in coordination with design leads and architects.
• Build and maintain verification test bench components and environments.
• Generate directed and constrained random tests.
• Run simulations and debug design and environment issues.
• Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• Craft automated verification flows for block and chip level verification.
• Apply knowledge of SystemVerilog, UVM, and logic simulators to verify complex designs.
• Collaborate with other engineers to ensure a robust verification flow.

Conhecimentos

SystemVerilog

UVM

Verilog

VHDL

Python

Perl

TCL

English (Fluent)

Formação académica

Bachelor's in EE or related field

Ferramentas

SystemVerilog

UVM

VHDL

Verilog

Python

Perl

TCL

Descrição da oferta de emprego

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!

The Silicon Engineering Group is responsible for developing cutting edge chips that can be found in all of your favourite Apple products. Our power management design team in Nabern (close to Stuttgart) has a unique opportunity for a motivated, collaborative, and solution-oriented intern to actively contribute to our chip development. We are looking for a Design Verification Intern in our team, who will enable bug‑free first silicon for our mixed‑signal designs, in close collaboration with our team of Digital and Analog Design engineers. The responsibilities involve all phases of pre‑silicon verification including establishing design verification methodology and test‑plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test‑writing, debug, coverage, sign‑off for RTL freeze and tape‑out.

• - You will develop verification plans in coordination with design leads and architects.
• - You’ll be responsible for building and maintaining verification test bench components and environments.
• - Generate directed and constrained random tests.
• - Run simulations and debug design and environment issues.
• - Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
• - Craft automated verification flows for block and chip level verification.
• - Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM), and logic simulators to verify complex designs.
• - Work with other block and core level engineers to ensure a flawless verification flow.
• - Work with Assertion Based Verification.

Minimum Qualifications

• Bachelors in EE or related field, or equivalent work experience
• Excellent communication and interpersonal skills, combined with the ability to collaborate
• Ability to work well on a team, take ownership and motivate self and others
• Fluent English skills (written and verbal)
• Good knowledge of SystemVerilog and UVM
• Experience with Python, Perl or TCL
• Good knowledge of Object Oriented Programming
• Available for 6 months or more

Preferred Qualifications

• Experience developing scalable and portable test‑benches
• Good understanding of digital design and basic knowledge of mixed signal verification