OpenHW Foundation HW Verification Engineer

The Eclipse Foundation Europe GmbH is hiring an HW Verification Engineer for its OpenHW Foundation. Working as a member of the Eclipse Research Team, the candidate will work to verify at industrial-grade open-source IPs based on RISC-V such as (but not limited to):

• Lock-step execution of dual-core systems based on CVA6
• Cache-coherency blocks
• Hypervisor ISA Extensions
• IO Memory-Management Units
• Advanced Interrupt Architecture

Through the OpenHW Foundation, we are recruiting for the role of HW Verification Engineer that will primarily contribute to the EU Rigoletto and/or Tristan project for the next 3 years. The Rigoletto project is an EU funded project that aims to create a RISC-V-based automotive hardware platform strongly linked with the formation of an open source, software-defined vehicle ecosystem led by European automotive manufacturers and suppliers. The project aligns with the high-level goal of EU Chips Joint Undertaking and of the industry-led Vehicle of the Future initiative.

The project will address SW to EDA tools, all the way to RTL components and demonstrators, ensuring a complete stack based on RISC-V. RIGOLETTO includes several work packages that will cover 1) requirements collections of the European market needs for Automotive Control- and Performance oriented CPUs; 2) architectural explorations and concept assessments for the different hardware components of the platform; 3-4) development and verification of industrial-grade CPUs and SoC building blocks defined in (1); 5) demonstration and validation of the main features of the automotive computing platform as its main computing components; 6-7) development of a RISC-V automotive ecosystem and supply-chain as well as commercial and licensing frameworks; 8) dissemination and exploitation.

A major focus for Rigoletto is to provide European digital sovereignty in the automotive market sector.

The Eclipse Foundation, and in particular, the OpenHW Foundation, provides industrial-grade open-source IPs thanks to its verification effort.

We are looking for a Hardware Verification Engineer who extends the Eclipse Foundation OpenHW Foundation and European ecosystem.

Location of the role:

You must be a resident of Italy, France, Spain, Belgium, Portugal, or Germany

In this role, you will:

• Use SystemVerilog and UVM to create and extend our testbenches: you should know how to verify IPs with random instructions
• Use GitHub to integrate and maintain everything open-source on GitHub under core-v-verif
• Verify CPUs and ISA extensions based on RISC-V
• Verify peripherals such as Advance Interrupt Architectures and IO MMU
• Verify cache-coherency and cache components
• Verify dual-core lock-step cache-coherent RISC-V systems
• Integrate and extend existing CPUs to support extra features
• Support the specific initiatives of the OpenHW Technical Working Group to drive interest, participation, and adoption beyond just the Rigoletto project
• Support the broader objectives of the Eclipse Foundation’s European research team, including
• Lead the activities of the Eclipse Foundation to support the European research ecosystem.
• Initiate and organize dissemination and community-building activities for the projects, leveraging existing Eclipse Foundation initiatives and assets
• Facilitate project participation at events such as conferences to benefit the projects
• Enable dissemination through web assets, newsletters and Eclipse-related social media
• Complete regular reporting (workload and expenses) as required by the EU processes
• Support research project developers in working with the Eclipse Development Process (EDP) and open source and open hardware best practices
• Represent the Eclipse Foundation and OpenHW Europe at research project meetings and reviews
• Encourage synergies among the EU projects and Eclipse Foundation members
• Work fully remotely in a large and global team

To accomplish the mission above, you should:

• Be very confident with SystemVerilog and UVM for use with coverage-driven, constrained-random verification strategies.
• Have a working knowledge of:

• Linux, Make, and Python
• Computer architectures of general-purpose CPUs
• Peripherals, bus protocols, interrupt controllers, MMUs
• Caches, coherency, and multicore systems
• Privilege RISC-V specifications
• A commercial SystemVerilog simulator and associated debug and coverage tools
• Familiarity with Formal Verification, RTL design, RISC-V ISA, and Git would also be an asset

Qualifications

• At least a Bachelor’s degree (or higher) in EE or CS with 5+ years of experience
• Fluent in English (spoken and written)

We offer highly competitive compensation along with a comprehensive benefits package. We thank all applicants for their interest; however, only those to be interviewed will be contacted. For more information about Eclipse Foundation, please visit our website at https://eclipse.org/

Eclipse respects the dignity and independence of people with disabilities, and is committed to providing accommodation and support to persons with disabilities throughout any recruitment process, once made aware of a need for accommodation. If you require any special accommodation or support during the recruitment process, please indicate in your email to us.