Hardware Verification Engineer (DE)

Codasip; München; Hybrid; EUR 50.000 - 90.000; Vollzeit

Zusammenfassung

Join a forward-thinking company at the forefront of processor solutions, specializing in the innovative RISC-V architecture. This role offers the chance to engage in cutting-edge technology, focusing on high-performance and energy-efficient CPU cores. As part of a dynamic team, you will work on the entire development lifecycle, from analysis to deployment, while collaborating with experienced developers across Europe. With a culture that values innovation and flexibility, this position promises a stimulating environment where your contributions will directly impact the future of processor technology. If you're passionate about RISC-V and eager to shape the future, this opportunity is perfect for you.

Leistungen

Flexible working hours

Hybrid working mode

31 days of holiday leave

Opportunity to work with RISC-V

Receptivity to innovations and ideas

Qualifikationen

• Experience with HW verification and simulation tools is essential.
• Knowledge of versioning tools like Git and proficiency in Linux are required.

Aufgaben

• Work on innovative processor optimization technology and RISC-V architecture.
• Participate in the entire development process from analysis to deployment.

Kenntnisse

HW verification

Simulation tools

UVM methodologies

Versioning tools (Git)

Linux

C++

Python

Self-organization

Reliability

Ausbildung

Ph.D.

MSc

B.Sc

University degree in Microelectronics

Tools

Git

Linux

HDL languages (Verilog, VHDL, System Verilog)

Jobbeschreibung

Welcome to Codasip

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient CPU cores from scratch, and our own automated proprietary tools to fully customize them. We give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

Our processor cores are based on the open RISC-V architecture. The potential for customizing RISC-V is unlocked with the Codasip Custom Compute approach: our unique architecture description language, CodAL, and the powerful automated processor design tool, Codasip Studio. These are at the heart of our unique and groundbreaking RISC-V processor solutions.

Founded in 2014, we've grown into a thriving and talented global community. Our IP engineering teams work from offices spread across Europe, including our first and largest design center in the beautiful city of Brno, Czechia. Across Europe, we already have design teams in Cambridge, Bristol, Munich, Villeneuve-Loubet, Barcelona, Thessaloniki, Heraklion and Athens. The Codasip team is also based close to its customers, which means we have dedicated sales and application engineers in the USA, Japan, Korea, and China.

Codasip is a European private company backed by well-funded EU grants. Our products are already making a real impact, with billions of devices in the market powered by our processor IP and tools.

• Department: Development IP
• Employment: Full-time
• Experience level: Mid-Senior (Ph.D./ MSc/B.Sc)
• Location: Germany (Preferably Munich)

YOU NEED TO POSSESS THE FOLLOWING KNOWLEDGE AND SKILLS:

• Experience with HW verification (simulation tools, formal tools, methodologies like UVM)
• Knowledge of versioning tools (Git - preferred) and Linux
• Software skills (C++ or Python preferred)
• Eagerness to constantly learn new things, active interest in the field, and self-education
• Self-organization and reliability

NICE-TO-HAVES:

• Desire to play a role in shaping the RISC-V world of tomorrow
• Knowledge of HDL languages (Verilog, VHDL, or System Verilog)
• Experience in Object-Oriented Programming and software engineering
• DIY activities related to open-source software, home automation, robotics, or similar
• University degree in a related field (Microelectronics, HW design, Embedded SW, Robotics or similar)

WHAT WE OFFER:

• Opportunity to work with RISC-V, computer architecture of the future
• Working on innovative and unique processor optimization technology (HLS)
• Participation in the whole development process from analysis to deployment
• Keeping in touch with the latest trends in the industry
• Opportunity to collaborate with experienced developers located within EU and UK
• Receptivity to your own innovations and ideas
• Freedom and trust from Codasip DNA
• Flexible working hours, including hybrid working mode (2 days office/ 3 days HO preferably)
• 31 days of holiday leave

SOME USEFUL LINKS ON CODASIP:

• Codasip RISC V Processor Solutions
• Design for differentiation: architecture licenses in RISC‑V
• Building a Swiss cheese model approach for processor verification
• Efficient verification of RISC-V processors – Technical paper

We're passionate about RISC-V processors. If you are, apply now :)