Principal Digital Verification Engineer

TN Germany; Deutschland; Vor Ort; EUR 80.000 - 120.000; Vollzeit

Zusammenfassung

A leading company is seeking a Principal Digital Verification Engineer to define and lead the development of the Digital Verification framework for complex digital and mixed-signal ICs. The role involves collaboration with designers, automation of processes, and leadership of the verification team to ensure high-quality product delivery.

Qualifikationen

• 10+ years of strong ASIC Verification experience.
• Proficiency in Digital Verification Industry Languages (UVM, System Verilog).
• Experience with power management DC-DC converters.

Aufgaben

• Define and develop UVM and System Verilog based Digital Verification environment.
• Lead the Digital Verification Team.
• Automate Digital Verification processes and scripting.

Kenntnisse

Leadership

Communication

Teamwork

Ausbildung

PhD in Electrical Engineering

BS in Electrical Engineering

MS in Electrical Engineering

Tools

TCL

Python

C/C++

Jobbeschreibung

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Job Description:

Job Summary:

A Principal Digital Verification Engineer will define and lead the development of the Digital Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management, and mixed signal functions.

MPS products include switching regulators, sensors, motor control, display drivers, audio amplifiers, and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital cameras, automobiles, and network equipment.

Essential Functions:

• Define and develop UVM and System Verilog based Digital Verification environment.
• Standardize, define, develop, and document VIPs.
• Integrate VIPs into the Project’s Digital Verification environment.
• Define Digital Verification Metrics for RTL and Gate-Level Verification.
• Develop Test Plans.
• Automate Digital Verification processes and scripting.
• Define, develop, and manage Regression infrastructure.
• Collaborate closely with Senior Digital and Analog Designers to develop VIP models.
• Lead the Digital Verification Team.
• Supervise Digital Verification Tasks across multiple projects.
• Review Verification Metrics and Results.
• Design Top-Level Tests for Digital Verification.
• Analyze and debug test results, code coverage, and functional coverage.
• Estimate, plan, and schedule Digital Verification activities to meet tape-out dates.

Qualifications:

• PhD/BS/MS in Electrical Engineering with emphasis on Digital Design/VLSI coursework.
• 10+ years of strong ASIC Verification experience.
• Experience with power management DC-DC converters and control topologies.
• Proficiency in Digital Verification Industry Languages (UVM, System Verilog) and Standards.
• Expertise in DV skills: constraint random tests, SV assertions, coverage metrics, DV modeling, test plans, regression analysis, UVM DV Agents, etc.
• Full knowledge of the Digital Design Flow: Specification, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG, AMS simulations.
• Proficiency with industry standard ASIC tools: simulators, synthesis, DFT, LEC, STA, etc.
• Strong scripting and automation skills in TCL, Python, or C/C++.
• Leadership skills to guide and mentor the DV team.
• Excellent communication and teamwork skills.
• Additional plus: experience with automotive standards, embedded MCU designs, or SoC development; Chinese language skills are highly desirable.