OpenHW Foundation HW Verification Engineer

Eclipse Foundation; Stuttgart; Remote; EUR 60.000 - 95.000; Vollzeit

Zusammenfassung

An innovative organization is seeking an HW Verification Engineer to join its dynamic research team. This exciting role involves verifying industrial-grade open-source IPs based on RISC-V, contributing to significant EU-funded projects aimed at enhancing the European RISC-V ecosystem and automotive hardware platforms. The ideal candidate will leverage their expertise in SystemVerilog and UVM to create robust testbenches and support the integration of cutting-edge technologies. Join a global team dedicated to promoting open hardware and making impactful contributions to the research community. This opportunity offers competitive compensation and the flexibility of remote work.

Qualifikationen

• 5+ years of experience in verification using SystemVerilog and UVM.
• Strong understanding of computer architecture and peripherals.

Aufgaben

• Create and extend testbenches using SystemVerilog and UVM.
• Verify CPUs, ISA extensions, and dual-core systems.

Kenntnisse

SystemVerilog

UVM

Linux

Python

Computer Architecture

RISC-V Specifications

Ausbildung

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Science

Tools

Git

Make

Jobbeschreibung

Job Title: HW Verification Engineer

The Eclipse Foundation Europe GmbH is hiring an HW Verification Engineer for its OpenHW Foundation. Working as a member of the Eclipse Research Team, the candidate will verify industrial-grade open-source IPs based on RISC-V, including:

• Lock-step execution of dual-core systems based on CVA6
• Cache-coherency blocks
• Hypervisor ISA Extensions
• IO Memory-Management Units
• Advanced Interrupt Architecture

This role involves contributing to the verification of the CVE2 core for the TRISTAN project and later switching to the Rigoletto project, both EU-funded initiatives aimed at advancing European RISC-V ecosystem and automotive hardware platforms.

Location: Italy, France, Spain, Belgium, Portugal, or Germany (resident only).

Responsibilities:

• Use SystemVerilog and UVM to create and extend testbenches, verifying IPs with random instructions
• Maintain open-source projects on GitHub under core-v-verif
• Verify CPUs, ISA extensions, peripherals, cache-coherency, and dual-core systems
• Support integration and extension of existing CPUs
• Participate in initiatives to promote interest and adoption of open hardware
• Support the European research ecosystem through dissemination, community activities, and representation at events
• Work remotely within a large, global team

Requirements:

• Strong proficiency in SystemVerilog and UVM for coverage-driven, constrained-random verification
• Knowledge of Linux, Make, and Python
• Understanding of computer architecture, peripherals, bus protocols, interrupt controllers, MMUs, caches, and multicore systems
• Familiarity with RISC-V specifications, formal verification, RTL design, and Git is a plus

Qualifications:

• Bachelor’s degree or higher in EE or CS with 5+ years of experience
• Fluent in English (spoken and written)

We offer competitive compensation and benefits. For more information, visit https://eclipse.org. Eclipse is committed to accessibility and supports accommodations for candidates with disabilities during the recruitment process.