PhD in digital design for in-memory computing accelerator ASICs

Fraunhofer-Gesellschaft; Dresden; Vor Ort; EUR 40.000 - 55.000; Vollzeit

Zusammenfassung

A leading research institute is seeking a doctoral student to develop AI hardware platforms. The role involves designing digital blocks, optimizing for efficiency, and contributing to SoC architecture. This position offers excellent supervision and networking opportunities, focusing on personal and professional growth.

Leistungen

Flexible working hours

Remote work options

Career development initiatives

Qualifikationen

• Completed scientific university studies in electrical engineering or comparable fields.
• Solid knowledge of ASIC/FPGA SoC architecture and digital design.
• Good written and spoken English skills.

Aufgaben

• Responsible for writing Verilog/VHDL code for AI blocks.
• Optimize design for power, performance, and area.
• Write research articles for journals and conferences.

Kenntnisse

Python

C

Digital Design

ASIC/FPGA SoC Architecture

Ausbildung

Master's or Diploma in Electrical Engineering

Tools

SystemVerilog

Verilog

VHDL

RC Compiler

Design Compiler

Cadence Genus

Innovus

Encounter

Jobbeschreibung

Everyone is talking about artificial intelligence. But who is developing the necessary chips? We are, for example!

Would you like to help drive the development of a new highly efficient AI hardware platform as a doctoral student? At Fraunhofer IPMS, in collaboration with renowned German and European partners from science and industry, we are developing analog accelerators using novel non-volatile memory chips! By merging logic and memory elements, costs and the required wafer area can be minimized, while energy efficiency and speed can be maximized. Specifically, in this project, we are using ferroelectric memories, which can calculate AI algorithms from the field of deep learning in resistive crossbar structures with extremely low power consumption and high speed.

Furthermore, we investigate and develop innovative memory solutions in advanced CMOS technologies such as FDSOI. The development of integrated circuits also plays an important role in making these networked devices and their implemented sensors locally intelligent. Alongside existing activities in sensor platform development, the institute is currently strengthening its expertise in embedded machine learning, neuromorphic hardware, and deep learning accelerators.

Want to get more information? Click here.

What you will do

1. Responsible for writing Verilog/VHDL code for AI blocks
2. Perform RTL design for digital blocks, including design, synthesis, and timing closure
3. Work independently through various phases of the RTL-to-GDS flow:
   1. focusing on hierarchical floor planning
   2. placement, clock tree generation
   3. routing and
   4. power distribution network generation for efficient timing closure and sign-off, including signal integrity
4. Optimize design for power, performance, and area (PPA)
5. Contribute to defining SoC architecture
6. Drive design reviews, create design documentation, and support post-silicon bring-up and debugging
7. Write research articles for journals and conferences

What you bring to the table

1. Completed scientific university studies in electrical engineering, electronics, communication engineering, information technology, or comparable fields with a master's or diploma degree
2. Solid knowledge of ASIC/FPGA SoC architecture and digital design
3. Proficiency in hardware description languages such as SystemVerilog, Verilog, or VHDL
4. Programming knowledge in Python and C
5. Experience with frontend and backend tools such as RC compiler, Design compiler, Cadence Genus, Innovus, Encounter
6. Prior knowledge in at least one of the following areas is advantageous:
   • deep learning
   • hardware development
   • memory technology
7. The ability to quickly familiarize yourself with new technical and scientific contexts
8. Highly motivated with a focus on producing high-quality scientific publications in peer-reviewed journals and presenting at international conferences
9. Good written and spoken English skills as a basis for working in an international team

What you can expect

We offer an exciting doctoral thesis with experienced supervision, focusing on your personal and professional development. As part of our doctoral college, you can network with other students and access seminars and lectures to support your research. This is an excellent opportunity to advance your career in applied research and potentially transition to a postdoc position at our institute.

Additionally, we offer female scientists the opportunity to participate in our TALENTA program: a comprehensive career and development initiative with tailored qualification offers. Find out more here.

We value diversity and promote work-life balance through flexible working hours and remote work options. We also emphasize thorough induction, an open environment, and opportunities for sports, music, and team events to foster team spirit.

The weekly working time is 39 hours, with part-time options available. The position is initially limited to 3 years. Employment as a postdoc is preferred. We welcome applications regardless of age, gender, nationality, ethnicity, religion, disability, sexual orientation, or identity. Severely disabled persons are given preference if equally qualified. Compensation is based on the TVöD collective agreement, with possible performance-based bonuses.

Fraunhofer plays a key role in developing vital future technologies and facilitating their industrial application, contributing to society through scientific excellence and innovation.

Interested? Apply online now. We look forward to meeting you!

Contact

Ms. Isabell Zwinscher
Human Resources

Telephone: [phone]

Mr. Dr. Thomas Kämpfe
Specialty Department

Telephone: [phone]

Fraunhofer Institute for Photonic Microsystems IPMS

www.ipms.fraunhofer.de

Requisition Number: 79643