Verification Engineer (m/f/d)

TN Germany; Neuried; Remote; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

A leading company in the semiconductor industry is seeking a Verification Engineer to develop and implement verification strategies for complex SoC and ASIC designs. The role offers significant remote work flexibility and requires expertise in UVM and SystemVerilog. Join a motivated team that values open communication and offers a high quality of life in a modern city.

Leistungen

30 days leave per year

High quality of life

Open communication

Remote work possible

Qualifikationen

• Solid experience in IP and SoC verification.
• Expertise in Specman E language and UVM methodology.
• Hands-on experience with SystemVerilog assertions.

Aufgaben

• Develop and implement verification strategies for complex SoC and ASIC designs.
• Create and maintain testbenches for functional verification.
• Analyze and debug design issues, collaborating with design and software teams.

Kenntnisse

Verification strategies

UVM

SystemVerilog

Debugging

Simulation

FPGA testing

Tools

Cadence tools

Xcelium

Specman-elite

SimVision

vManager

Jobbeschreibung

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Verification Engineer (m/f/d)

Employment with Hays Professional Solutions GmbH Neuried
Start date: asap
Reference number: 821993/1

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About the company

Location: Remote (70-90%)

Responsibilities

1. Develop and implement verification strategies for complex SoC and ASIC designs
2. Create and maintain testbenches for functional verification
3. Apply verification methodologies such as UVM, SystemVerilog, or VHDL
4. Analyze and debug design issues, collaborating closely with design and software teams
5. Conduct simulations and generate verification reports
6. Support the development of verification automation and scripting
7. Perform validation and testing on FPGA and hardware prototypes

Profile

1. Solid experience in multiple project verification sign-off (both IP and SoC verification)
2. Specman E language and UVM methodology expertise
3. Hands on experience with SystemVerilog assertions
4. Understanding of ARM-AMBA protocols, Verilog constructs to debug RTL issues and C++ constructs to debug TLM models
5. Working experience with Cadence simulation/regression tools (Xcelium, Specman-elite, SimVision, vManager)
6. Experience on requirement-based verification for ISO/safety projects
7. Experience with Graphics processing IPs, formal property checking, and other automated tools
8. For initial setup and kick-off, visiting the SNEU office is desirable
9. For reviews and critical deliverables, future visits to SNEU might be required

Benefits

• 30 days leave per year
• A city with a high quality of life that embraces both modern and traditional values
• A highly motivated team and open communication
• Remote work is possible