Digital Verification Engineer (Specman) – Semiconductor (all gender)

ALTEN Germany; München; Vor Ort; EUR 50.000 - 70.000; Vollzeit

Benefits dieser Stelle

Flexible working hours

Mobile working options

Corporate benefits

Team events

Zusammenfassung

A leading engineering service provider is seeking a Digital Verification Engineer to verify mixed-signal designs and create verification concepts. The role requires an engineering degree and experience in digital functional verification, with strong skills in System Verilog and UVM methodology. The position offers a full-time contract in Munich, promoting career development and work-life balance.

Qualifikationen

• Completed an engineering degree in a relevant field.
• Practical experience in digital functional verification.
• Extensive programming skills in System Verilog and assertions.
• Good knowledge of UVM methodology and Specman-e language.
• Ability to interpret RTL and gate-level code.

Aufgaben

• Verify mixed-signal designs on block and system level.
• Interpret product requirements to create verification concepts.
• Perform random-constraint testbenches.
• Create assertions using formal methods.
• Collaborate with engineers across multiple sites.

Kenntnisse

Digital functional verification

System Verilog programming

UVM methodology knowledge

Scripting languages (Python, Perl)

Communication skills in English

Ausbildung

Engineering degree in electrical engineering or computer science

Jobbeschreibung

Digital Verification Engineer (Specman) – Semiconductor (all gender)

As one of the world's leading engineering service providers, we at ALTEN are committed to positively shaping the future of our partners, the careers of our employees and the challenges facing our society and environment.

Job Description

• Verify mixed‑signal designs on block and system level resting upon formal and functional verification
• Interpret product requirements to create the verification concept and the product verification specification
• Perform random‑constraint testbenches according to the state of the art
• Create assertions to prove the design using formal methods
• Work in collaboration with lab and test engineers, designers, system architects, and verification engineers across multiple sites

Qualifications

• Have completed an engineering degree in electrical engineering, computer science or similar studies
• Already have practical experience in the field of digital functional verification and common safety standards
• Have extensive programming skills in coding in System Verilog and System Verilog assertions
• Have good knowledge of UVM methodology and Specman‑e language, scripting languages like Python or Perl, and ability to interpret RTL and gate‑level code
• Have good communication skills in English

We value diversity and therefore welcome all applications – regardless of gender, nationality, ethnic and social origin, religion/belief, disability, age and sexual orientation and identity. Severely disabled persons will be given preferential consideration if they are equally qualified.

Additional Information

• Talent Management – we develop your career
• Work life balance – flexible working hours and mobile working possible
• Fit and relaxed – with EGYM Wellpass
• Enjoy biking – always on tour with bike leasing
• Green Mobility – with us you can travel at a reduced rate

In addition we offer a permanent employment contract, corporate benefits and team events.

Job Details

• Seniority level: Entry level
• Employment type: Full‑time
• Job function: IT Services and IT Consulting

Contact

Do you have any questions? Then contact me: Özlem Mumin (Tel.: [phone])

Or apply now using our online application form.