Digital IP Design Engineer (f/m/d)

NXP Semiconductors; München; Vor Ort; EUR 110.000 - 140.000; Vollzeit

Zusammenfassung

NXP Semiconductors in Munich seeks a Senior Digital IP Design Engineer to develop and integrate RTL blocks for complex mixed-signal SoCs, aligning with architectural specifications and performance targets.

You will collaborate across hardware and software teams, perform design verification, timing analysis, and ensure DFT readiness, while advancing IP for AI/ML accelerators and RISC-V cores through the full development lifecycle. Strong English communication is essential.

Qualifikationen

• Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related field.
• Minimum 10 years of experience in IP or subsystem design.
• Solid understanding of microprocessor architecture, interconnects, and cache coherency.
• Hands-on experience with CPU design (proprietary cores, RISC-V, or AI/ML accelerators).
• Experience in using AI-based tools to enhance development and design efficiency.
• Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
• Advanced knowledge of Verilog, SystemVerilog, and C/C++.
• Proficiency in scripting languages such as Python, Perl, TCL, or Shell.
• Experience in debugging designs in both pre-silicon and post-silicon environments.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills in English.
• Basic conversational German is a plus.

Aufgaben

• Develop and implement digital IP and logic designs for complex Mixed-Signal SoCs, adhering to architectural specifications and performance requirements.
• Collaborate closely with hardware and software teams, as well as architecture and system engineering teams, to understand IP functionality and system-level use cases to define features, interfaces and integrate digital blocks.
• Develop high-quality, area-optimal, low-power RTL design using industry-standard hardware description languages (Verilog/SystemVerilog).
• Complete design quality checks such as Lint, CDC/RDC, etc. using industry-standard tools.
• Conduct IP-level design verification activities, including basic testbench development, simulation and debugging to ensure functional correctness.
• Complete IP synthesis and basic timing analysis to meet timing, area and power targets.
• Ensure IP design implementation is done according to design for testability (DFT) requirements.
• Generate comprehensive design documentation and participate in design reviews.
• Troubleshoot and resolve design issues throughout the development lifecycle.
• Stay updated with the latest industry trends, tools, and methodologies in digital design.

Kenntnisse

Verilog/SystemVerilog

C/C++

Python

AMBA protocols (AHB, AXI, ACE, CHI)

CPU design (RISC-V, AI/ML accelerators

Debugging & testbench

English communication

German language (basics)

Ausbildung

Bachelor's or Master’s degree in Electrical Engineering, Computer Science, or related field

Tools

Python

Jobbeschreibung

Business Line Description

Advanced Chip Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, micro-controllers, and networking. The Munich Digital IP team develops interface components, DSP subsystems, next generation AI/ML core and RISCV IPs.

Key Responsibilities

• Develop and implement digital IP and logic designs for complex Mixed-Signal System-on-Chips (SoCs), adhering to architectural specifications and performance requirements.
• Collaborate closely with hardware and software teams, as well as architecture and system engineering teams, to understand IP functionality and system-level use cases to define features, interfaces and integrate digital blocks.
• Develop high-quality, area-optimal, low-power RTL design using industry-standard hardware description languages (Verilog/SystemVerilog).
• Complete design quality checks such as Lint, CDC/RDC, etc. using industry-standard tools.
• Conduct IP-level design verification activities, including basic testbench development, simulation and debugging to ensure functional correctness.
• Complete IP synthesis and basic timing analysis to meet timing, area and power targets.
• Ensure IP design implementation is done according to design for testability (DFT) requirements.
• Generate comprehensive design documentation and participate in design reviews.
• Troubleshoot and resolve design issues throughout the development lifecycle.
• Stay updated with the latest industry trends, tools, and methodologies in digital design.

Qualification

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
• Minimum 10 years of experience in IP or subsystem design.
• Solid understanding of microprocessor architecture, interconnects, and cache coherency mechanisms.
• Hands-on experience with CPU design (proprietary cores, RISC-V, or AI/ML accelerators).
• Experience in using AI-based tools to enhance development and design efficiency.
• Experience with AMBA protocols (AHB, AXI, ACE, CHI) and memory systems (ROM, RAM, Flash, DDR/LPDDR).
• Advanced knowledge of Verilog, SystemVerilog, and C/C++.
• Proficiency in scripting languages such as Python, Perl, TCL, or Shell.
• Experience in debugging designs in both pre-silicon (simulation/emulation/FPGA) and post-silicon environments.
• Strong analytical and problem-solving skills.
• Excellent written and verbal communication skills in English.
• Basic conversational German is a plus.

Please note: The successful candidate may/will be responsible for security related tasks. The assignment may/will be in scope of security certifications, therefore a conscious and reliable way of working is necessary.

More information about NXP in Germany... #LI-3da9

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Bright Minds. Bright Futures.

We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP

We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress.

Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Thank you for considering a career at NXP.

To help you prepare for the different steps in our hiring process, see the following useful advice and tips.

Thank you for your interest in supporting our recruitment efforts. Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise.