Digital Design Engineer

European Tech Recruit; Aachen; Vor Ort; EUR 58.000 - 85.000; Vollzeit

Zusammenfassung

A leading recruitment firm in the Aachen area is seeking a Digital Design Engineer to contribute to high-performance digital and mixed-signal IC development. The ideal candidate will have strong expertise in RTL design using SystemVerilog/VHDL and experience with EDA tools. This role offers full-time employment for professionals at the mid-senior level within the semiconductor industry.

Qualifikationen

• Strong proficiency in RTL design using SystemVerilog/VHDL.
• Experience with EDA tools for logic synthesis and analysis.
• Hands-on experience in physical implementation.

Aufgaben

• Own RTL design and micro-architecture of digital subsystems.
• Develop and optimize backend flow including synthesis and timing closure.
• Generate documentation and support post-silicon bring-up.

Kenntnisse

RTL design using SystemVerilog/VHDL

Digital verification

Scripting (Python, Tcl)

EDA tools (Cadence, Synopsys, Mentor)

Low-power design techniques

Problem-solving skills

Attention to detail

Tools

EDA tools (Cadence, Synopsys, Mentor)

Jobbeschreibung

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Principal Consultant | Software Engineering, AI & CV/ML, Semiconductors & Electronics

European Tech Recruit are working closely with an exciting semicon company, based in the Aachen area, who are looking for a a number of Digital Design Engineers with strong expertise in either frontend RTL design or backend physical implementation to join their team.

In this role you will contribute to the development of high-performance digital and mixed signal ICs in advanced technology nodes such as 22FDX and other FinFET/FD-SOI processes.

Responsibilities as Digital Design Engineer:

• Own RTL design and micro-architecture of digital subsystems (e.g., DSP blocks, control logic, interfaces).
• Develop and optimize backend flow, including synthesis, floorplanning, placement and routing (P&R), timing closure, and signoff (STA, LVS, DRC).
• Perform logic synthesis and work with physical design teams to ensure a clean handoff and alignment across digital and mixed-signal boundaries.
• Support integration of digital blocks with analog/mixed-signal subsystems.
• Generate documentation, testbenches, and support post-silicon bring-up and debugging.
• (Senior level) Lead block-level architecture, mentor junior designers, and guide design methodology decisions.

Requirements:

• Strong proficiency in RTL design using SystemVerilog/VHDL, digital verification, and scripting (Python, Tcl, etc.).
• Experience with EDA tools from Cadence, Synopsys or Mentor for logic synthesis, static timing analysis, and backend implementation.
• Familiarity with low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design.
• Hands-on experience in physical implementation (floorplanning, P&R, CTS, STA, DRC, LVS).
• Experience with modern process nodes, especially 22FDX, 16/12nm FinFET, or similar.
• Good understanding of mixed-signal integration, top-level assembly, and testability concepts (DFT is a plus).
• Strong problem-solving skills, attention to detail, and ability to work independently.

If this role is of any interest please apply directly on LinkedIn or send a copy of your CV to [e-mail].

By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice/)

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Engineering, Information Technology, and Design

• Industries

  Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development

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