Cellular SoC Frontend-STA Engineer

TN Germany; München; Vor Ort; EUR 60.000 - 100.000; Vollzeit

Zusammenfassung

An innovative firm is seeking a Frontend-STA engineer to join their Cellular SoC Integration team in Munich. This exciting role involves working on cutting-edge designs and sophisticated technology nodes, focusing on constraint development and timing analysis. You will collaborate with talented designers to ensure sign-off quality of timing constraints while optimizing power, performance, and area. If you're passionate about technology and eager to make a significant impact in a dynamic environment, this opportunity is perfect for you.

Qualifikationen

• Hands-on experience with constraint development and analysis.
• Proficient in scripting languages and industry-standard STA tools.

Aufgaben

• Responsible for constraint development and sign-off STA.
• Collaborate with digital and physical design teams for optimization.

Kenntnisse

Constraint Development

STA Tools (PrimeTime, Tempus)

Scripting Languages (TCL, Perl, Shell)

Linux

Verilog

RTL/Netlist Analysis

Communication Skills

Tools

PerForce

Jobbeschreibung

Social network you want to login/join with:

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Client:

Apple

Location:

Job Category:

-

EU work permit required:

Yes

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Job Reference:

95f9570ddc79

Job Views:

2

Posted:

05.05.2025

Expiry Date:

19.06.2025

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Job Description:

Summary:
Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices, strengthening our dedication to leave the world better than we found it. In this role, you will be a key part of the Cellular SoC Integration team in Munich, Germany. As a Frontend-STA engineer, you are the focal point for constraints development as well as design- and timing analysis. Together with RTL designers, Physical designers, and other integration teams, you will work on very exciting designs and sophisticated technology nodes.
Key Qualifications:

• Hands-on experience on multiple projects with constraint development, analysis, and debugging.
• Experience with industry-standard tools for STA, e.g., PrimeTime or Tempus.
• Good understanding of hierarchical design approaches, top-down design, timing budgeting, and timing and physical convergence.
• Proficient in scripting languages (TCL, Perl, shell), Linux, and revision control systems (e.g., PerForce).
• Good understanding of Verilog and RTL/Netlist analysis.
• Experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs, and power optimizations is a plus.
• Experience with synthesis, logic equivalence, or ECO techniques is a plus.
• Good communication skills and ability to find effective technical solutions between RTL-Design and Physical-Design teams.
• English language proficiency is required.

Description:
You will be responsible for constraint development, including deliveries for synthesis, PnR, and sign-off STA. You will work on partition- as well as SoC-level and verify the results post-synthesis for all STA modes. In this role, you will be the link between digital design, mixed-signal design (.lib definition), and physical design. Your responsibility is to achieve sign-off quality of timing constraints based on stakeholder requirements. You will closely collaborate with digital designers to understand the design intent and its clock structure to optimize power, performance, and area. You will work with CAD and PD teams to continuously improve development flows.