ASIC/FPGA Design & Verification Specialist – RISC-V Architectures (m/f/d)

FAU Erlangen-Nürnberg; Erlangen; Vor Ort; EUR 50.000 - 65.000; Vollzeit

Zusammenfassung

A leading research university in Erlangen is seeking an ASIC/FPGA Design & Verification Specialist focused on RISC-V architectures. The role involves designing hardware accelerators and developing methods for low-power IoT nodes, alongside supervising academic theses. Candidates should possess a Master's degree in a related field and have strong skills in SystemVerilog or VHDL. This position offers substantial benefits and encourages continuous professional development.

Leistungen

30 days annual leave

Occupational pension scheme

Flexible working hours

Subsidized food and drinks

Career development programs

Qualifikationen

• Completed academic degree in digital circuit technology or related field.
• Good knowledge of SystemVerilog and/or VHDL.
• Knowledge about FPGA design flows as well as ASIC design flows from RTL to GDS.

Aufgaben

• Design integrated hardware accelerators for machine learning in RISC-V subsystems.
• Develop hardware for battery-powered IoT nodes with RISC-V processor subsystem.
• Optimize architectures for energy-efficient hardware accelerators.

Kenntnisse

SystemVerilog

VHDL

FPGA design flows

ASIC design flows

English proficiency

Ausbildung

Master's degree in digital circuit technology or related field

Jobbeschreibung

ASIC/FPGA Design & Verification Specialist – RISC-V Architectures (m/f/d)

ASIC/FPGA Design & Verification Specialist – RISC-V Architectures (m/f/d)

• Integrated hardware accelerators for machine learning in RISC-V subsystems
• Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption
• Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a System-on-Chip with a RISC-V
• Methods and strategies for efficient functional and formal digital verification, including the emulation of digital System-on-Chip (SoC) with RISC-V and mixed-signal IPs
• Expansion of collaboration with the Fraunhofer IIS and other institutes in the field
• Publication and presentation of research results
• Supervision of Bachelor's and Master's theses, as well as conducting teaching exercises, seminars, or computer labs
  
  

Your Tasks

• Integrated hardware accelerators for machine learning in RISC-V subsystems
• Hardware and hardware-related software for methods and strategies for battery-powered IoT nodes with an optimized RISC-V processor subsystem for ultra-low power consumption
• Hard- and software co-optimized architectures and strategies for high-performance, energy-efficient hardware accelerators, as well as a System-on-Chip with a RISC-V
• Methods and strategies for efficient functional and formal digital verification, including the emulation of digital System-on-Chip (SoC) with RISC-V and mixed-signal IPs
• Expansion of collaboration with the Fraunhofer IIS and other institutes in the field
• Publication and presentation of research results
• Supervision of Bachelor's and Master's theses, as well as conducting teaching exercises, seminars, or computer labs
  
  

Your Profile

• Completed academic degree (Master's/Diploma) in digital circuit technology or a related field
• The duties require you to comply with US Export Restrictions (EAR) -->
• Good knowledge of SystemVerilog and/or VHDL
• Knowledge about FPGA design flows as well as ASIC design flows from RTL to GDS
• Excellent English skills
  
  

Benefits: We Have a Lot To Offer

• Regular promotion to the next level and increase in salary pursuant to the collective bargaining agreement for the public service of the German Länder (TV-L) or remuneration pursuant to the Bavarian Public Servants Remuneration Act (BayBesG) plus an additional annual bonus
• 30 days annual leave at five working days per week with additional free days on December 24 and 31
• Occupational pension scheme and asset accumulation savings scheme
• Excellent support during the academic qualification phase
• Systematic career development in collaboration with the Graduate Center
• Thorough onboarding process with a dedicated team
• Subsidized food and drinks in our student restaurants
• Place of work within comfortable walking distance of public transport
• Family-friendly environment with childcare options, also during school holidays
• Flexible working hours
• A wide range of training courses and opportunities for professional development
  
  

PaymentTV-L E 13

• Beschäftigungsverhältnis

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