ASIC Design Verification Technical Lead imec Germany

imec; Heilbronn; Vor Ort; EUR 110.000 - 170.000; Vollzeit

Zusammenfassung

imec, a world-leading research hub in nanoelectronics, seeks an ASIC Design Verification Technical Lead for its Heilbronn site in Germany. You will lead a multidisciplinary DV team, define verification strategies, and drive complex SoC verification using UVM, SystemVerilog, and constrained random techniques.

You will create reusable VIP, build verification flows, and oversee both RTL and VIP debugging, while coordinating internal and external DV engineers.

Qualifikationen

• BSc or MSc in electronics engineering with 10+ years of relevant experience.
• Demonstrated experience with digital verification: verification plan definition, verification methodologies (UVM), code/functional coverage, formal verification, constrained random verification, verification plan execution and tracking.
• Strong experience with digital circuit design in (System) Verilog and checks, e.g. LINT, CDC and RDC.
• Experience with complex SoC subsystems such as high-speed interfaces, CPU, accelerator cores, peripherals integration, etc.
• Experience with complex bus systems, memory hierarchies and instruction set architectures are preferred.
• Experience with CPU software development environments.
• Understanding of the remaining steps of the digital ASIC-design flow is required: (low) lower simulations, logic synthesis, timing analysis, logic equivalence, DFT and/or P&R.
• Knowledge of FPGA development is a plus.
• Experience with scripting languages like TCL, Matlab and Python is required.
• Experience with revisioning systems, like git is required.
• Automotive quality experience is required.
• Structural way of working and ability to develop and manage activity planning is highly preferred.
• Previous experience working closely with (internal or external) stakeholders is a plus.
• Able to take initiative and responsibility for team’s success. Thinking pro-actively, working independently and having a creative problem-solving attitude are attributes that define yourself.
• Have broad interest across disciplines and like to embrace new challenges.
• Excellent communication skills in English (written and spoken).

Aufgaben

• Create verification plan that meets the requirements.
• Drive requirements and verification review meetings.
• Understand complex functional subsystems, associated standards and VIP.
• Contribute to defining and implementing the verification methodology and infrastructure.
• Create VIP, with reuse in mind.
• Contribute to creating flows for and executing debugging of both RTL and the VIP.
• Manage internal and external teams of DV engineers.
• Manage UPF based low power verification flows.

Kenntnisse

Digital verification

UVM

Code coverage

Formal verification

Constrained random verif

SystemVerilog

Verilog

Scripting TCL

Python

Matlab

Git

CPU software

SoC subsystems

English fluency

Automotive quality

Ausbildung

BSc or MSc in electronics engineering

Tools

Git

Jobbeschreibung

imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology is what makes us unique. By leveraging our world class infrastructure and local and global ecosystem of partners across a multitude of industries, we create ground-breaking innovation in a wide range of application domains.

Our new site in Heilbronn, Germany, is a strategic innovation node in imec’s European expansion. It aims to foster a vibrant ecosystem of startups, corporates, and research institutions focused on deep tech innovation, e.g. for an open chiplet ecosystem. To support this mission, we are looking for a ASIC Design Verification Technical Lead for imec Heilbronn.

What you will do

We need you as an ASIC Design Verification Technical Lead to be part of our multidisciplinary team to:

• Create verification plan that meets the requirements.
• Drive requirements and verification review meetings.
• Understand complex functional subsystems, associated standards and VIP.
• Contribute to defining and implementing the verification methodology and infrastructure.
• Create VIP, with reuse in mind.
• Contribute to creating flows for and executing debugging of both RTL and the VIP.
• Manage internal and external teams of DV engineers.
• Manage UPF based low power verification flows.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its local footprint in Heilbronn, Germany. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• BSc or MSc in electronics engineering with 10+ years of relevant experience.
• Demonstrated experience with digital verification: verification plan definition, verification methodologies (UVM), code/functional coverage, formal verification, constrained random verification, verification plan execution and tracking.
• Strong experience with digital circuit design in (System) Verilog and checks, e.g. LINT, CDC and RDC.
• Experience with complex SoC subsystems such as high-speed interfaces, CPU, accelerator cores, peripherals integration, etc.
• Experience with complex bus systems, memory hierarchies and instruction set architectures are preferred.
• Experience with CPU software development environments.
• Understanding of the remaining steps of the digital ASIC-design flow is required: (low) lower simulations, logic synthesis, timing analysis, logic equivalence, DFT and/or P&R.
• Knowledge of FPGA development is a plus.
• Experience with scripting languages like TCL, Matlab and Python is required.
• Experience with revisioning systems, like git is required.
• Automotive quality experience is required.
• Structural way of working and ability to develop and manage activity planning is highly preferred.
• Previous experience working closely with (internal or external) stakeholders is a plus.
• Able to take initiative and responsibility for team’s success. Thinking pro-actively, working independently and having a creative problem-solving attitude are attributes that define yourself.
• Have broad interest across disciplines and like to embrace new challenges.
• Excellent communication skills in English (written and spoken).

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee-based referral services and recruiting agencies (hereafter "Agency") to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.