Analog Design Engineer

Kandou Ai; Saint-Sulpice; Vor Ort; CHF 110.000 - 170.000; Vollzeit

Zusammenfassung

Kandou is redefining AI hardware economics with a chiplet-based, energy-efficient memory fabric. We seek an Analog Design Engineer to lead design, modeling, and verification of high-speed Serdes in advanced nodes, collaborating across architecture, layout, and verification teams.

Requirements include a Master’s/PhD in Electronics and 5+ years in analog design, with Cadence Virtuoso and Ocean/MDL experience. Join us in a frontier role at the intersection of AI and semiconductor innovation.

Qualifikationen

• Master's or PhD in Electronics or related field.
• 5+ years in analog design and layout of high-speed circuits.
• Experience with multi-gigabit data-link transceivers or RF.
• Proficiency with Cadence Virtuoso and silicon validation.

Aufgaben

• Design, model, and verify custom analog designs for high-speed Serdes.
• Verify analog circuits to meet architecture specs and flows.
• Support customers on requirements, performance results, and delivery.
• Assist analog IP integration and cross-functional collaboration.

Kenntnisse

Analog design

Serdes circuits

DFT/DFM/ESD

Layout techniques

EDA tools

Oscillators/PLL

Team collaboration

Ausbildung

Master's/PhD in Electronics

Tools

Cadence Virtuoso

Ocean/MDL

Jobbeschreibung

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.

Job title: Analog Design Engineer

Location: EU/CH/UK

Key Responsibilities

• Position in design, modeling, and verification of custom analog designs for high-speed Serdes transceivers in advanced technology nodes
• Design and verification of analog circuits, following prescribed design and documentation flows, to meet architecture specifications
• If necessary, support and interact with customers on requirements, design specifications, performance results and product delivery
• Support analog IP and chip level integration
• Collaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation and quality teams as needed

Competencies

• Skilled in the design of high speed analog serdes circuits including DFT, DFM and ESD protection, with a deep knowledge of transistor and wireline communications fundamentals
• Understanding of layout approaches and design techniques used for high-speed and high precision circuits
• Advanced user of EDA tools for design and verification of analog circuits, preferably using the Cadence Virtuoso environment, including their use for simulation, parasitic extraction, electromagnetic modelling, EM/IR and reliability analysis as well as LVS and DRC
• Self-motivated, a strong sense of ownership and responsibility with good verbal and written communication skills and a team player
• Ability to manage and complete designs to schedule using defined design process flows as well as reporting design status to internal management team

Requirements

• The candidate should have a Master's or Ph.D. degree in Electronics or other relevant fields
• Minimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC’s, serialisers and output drivers etc.
• Expertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, amplifiers, buffers, regulators, filters, ADC, DAC etc.
• Experience with modern semiconductor process technologies, preferably in finFet technology nodes
• Experience using Ocean, MDL or equivalent to automate analog design verification is highly desirable