Digital Design Engineer for High-Speed AI IPs

Kandou AI; Saint-Sulpice; Vor Ort; CHF 150.000 - 190.000; Vollzeit

Zusammenfassung

Kandou in Lausanne, Switzerland, is seeking an Advanced R&D - Digital Design Engineer to design and implement the digital sub-systems of our high-speed communication IPs — background calibration engines, adaptation loops, DSP kernels, FEC blocks, and control state machines — in advanced FinFET nodes.

You will bridge system-level algorithms with mixed-signal front-ends and own RTL through synthesis, timing closure, and low-power sign-off.

Qualifikationen

• 5+ years designing high-speed, power-efficient digital systems for wireline or wireless communications.
• Strong background in high-speed digital architectures and CMOS/FinFET.
• Experience with synthesis, timing, and verification flows.

Aufgaben

• Own RTL design, synthesis, timing closure, and functional verification of assigned digital blocks.
• Define block-level architecture with system architects and analog designers.
• Integrate blocks with DFT, low-power, and physical design flows.
• Support post-silicon bring-up, debug, validation, and productization.
• Contribute to design and analysis of communication algorithms (modulation, calibration, encoding/decoding).
• Produce clear design, verification, and progress reports.

Kenntnisse

SystemVerilog

Python scripting

Analytical skills

Team player

Ausbildung

Masters or Ph.D. in E.E., Communications or related field

Tools

Cadence Genus/Innovus

DC/ICC2

Xcelium

Spyglass

PrimeTime

Python for automation

Jobbeschreibung

Kandou in Lausanne, Switzerland, is seeking an Advanced R&D - Digital Design Engineer to design and implement the digital sub-systems of our high-speed communication IPs — background calibration engines, adaptation loops, DSP kernels, FEC blocks, and control state machines — in advanced FinFET nodes.

You will bridge system-level algorithms with mixed-signal front-ends and own RTL through synthesis, timing closure, and low-power sign-off.