Compiler Architect for AI Hardware & Co-Design

microTECH Global Limited; Zürich; Hybrid; CHF 110,000 - 180,000; Full time

Job summary

microTECH Global Limited is seeking a highly capable researcher to explore compiler technologies and toolchains for next-generation architectures, including CPUs and AI accelerators. You will evaluate software-hardware co-design trade-offs in collaboration with cross-functional experts.

The role covers design and validation of efficient compiler infrastructures, kernel fusion, memory layout tuning, and operator scheduling for GPUs and custom accelerators.

Qualifications

• MSc or PhD in Computer Science, Software Engineering, or a related field.
• At least 1 year of relevant experience in compiler development, system software, or computer architecture.
• Proven expertise in compiler construction covering front end parsing, middle end optimizations, and back end code generation.
• Strong background with LLVM, GCC and/or modern deep learning compilers (MLIR, TVM, XLA).
• Solid fundamentals in traditional optimizations and AI-specific techniques; experience with code generation for specialized hardware.

Responsibilities

• Technology Research – design and validate efficient compiler infrastructures and algorithms.
• Software-Hardware Co-Optimization – drive co-optimization including kernel fusion, memory layout tuning, and operator scheduling.
• Technology Insight – track compiler ecosystem trends and propose new technologies to improve speed, size, and programmability.
• External Collaboration – lead research collaboration projects with academic and industrial partners.

Skills

Compiler development

C/C++

Python

English fluency

Performance optimization

System software

Hardware acceleration

Education

MSc or PhD in CS/SE

Tools

LLVM

GCC

MLIR

TVM

XLA

Job description

microTECH Global Limited is seeking a highly capable researcher to explore compiler technologies and toolchains for next-generation architectures, including CPUs and AI accelerators. You will evaluate software-hardware co-design trade-offs in collaboration with cross-functional experts.

The role covers design and validation of efficient compiler infrastructures, kernel fusion, memory layout tuning, and operator scheduling for GPUs and custom accelerators.