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Staff Design Verification Engineer
Résumé du poste
A leading company is looking for a Staff Design Verification Engineer to design and verify advanced DSPs, contributing to innovative digital products. This hybrid role requires a deep understanding of SerDes, DSP cores, and ASIC verification processes. Candidates should hold a relevant degree and have extensive verification experience, with opportunities for mentorship and professional development.
Qualifications
- Minimum of 9 years of ASIC design verification experience.
- Strong experience building reusable testbenches with advanced debugging expertise.
- Familiarity with digital verification methodologies.
Responsabilités
- Architect, design, and verify DSPs using high-speed mixed-signal PHYs.
- Own the full verification lifecycle and collaborate with design teams.
- Mentor junior engineers and contribute to technical excellence.
Connaissances
Formation
Outils
Staff Design Verification Engineer
Our client accelerates the future of digital innovation by powering mission-critical data communication—supporting everything from AI to seamless video streaming to the metaverse. Their technology fuels advancements across data-intensive industries including data centers, storage, networking, AI, 5G infrastructure, and autonomous vehicles. Known for their innovation and reliability, they partner with industry leaders to shape the next generation of digital products.
What You’ll Do
Architect, design, and verify DSPs using high-speed mixed-signal PHYs such as PCIe and Ethernet.
Contribute to protocol development across various new variants—roles available across multiple focus areas.
Build scalable UVM testbench components for verifying complex RTL and firmware functionality.
Demonstrate in-depth understanding of SerDes and DSP cores; write test cases to optimize component control.
Own the full verification lifecycle—from creating and reviewing verification plans to implementation and sign-off for tape-out.
Collaborate with the design team to define verification requirements and scope of key features.
Mentor junior engineers and contribute to a culture of technical excellence.
What You’ll Need
Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related discipline.
Minimum of 9 years of ASIC design verification experience.
Strong hands-on experience building reusable testbenches with advanced debugging expertise.
Proficiency in SystemVerilog and UVM.
Familiarity with leading EDA tools and methodologies used in digital verification.
This is a hybrid role based in Ontario, with a preference for candidates located near the GTA or Ottawa.
Bonus Points For
Experience with SerDes.
Knowledge of Ethernet and/or PCIe protocols.
Familiarity with CMIS standards.
Understanding of protocols such as I2C, SPI, USB, NVMe, APB, AHB, etc.
Experience working with RISC-V microcontrollers.
Please reach out to nick.weiszhaar@talentlab.com with your resume if you're a fit for the position and interested in learning more.
* Le salaire de référence se base sur les salaires cibles des leaders du marché dans leurs secteurs correspondants. Il vise à servir de guide pour aider les membres Premium à évaluer les postes vacants et contribuer aux négociations salariales. Le salaire de référence n’est pas fourni directement par l’entreprise et peut pourrait être beaucoup plus élevé ou plus bas.