UVM Verification Engineer - SystemVerilog / Verilog / OVM

USA Tech Recruit; Ottawa; Hybrid; CAD 80,000 - 120,000; Full time

Job summary

An established industry player is seeking a seasoned UVM Verification Engineer with over a decade of experience in ASIC verification. This role involves leading verification activities, documenting test cases, and employing advanced verification techniques. The company offers a hybrid work model in Ottawa, encouraging both local and international applicants to join their dynamic team. If you're passionate about semiconductor design and looking to make a significant impact in a collaborative environment, this opportunity is perfect for you.

Qualifications

• 10+ years of experience in ASIC verification is essential.
• Highly skilled in Verilog, SystemVerilog, and scripting languages.

Responsibilities

• Prime verification activities for blocks or entire chips.
• Document test environments and write test cases.

Skills

ASIC verification

Verilog

SystemVerilog

OVM/UVM methodologies

scripting languages

constrained random verification techniques

functional coverage

Job description

UVM Verification Engineer - SystemVerilog / Verilog / OVM

1 week ago Be among the first 25 applicants

Are you a senior Verification Engineer with 10+ years' industry experience?

We are partnered with an Ottawa HQ'd ASIC design house offering augmented design services and turnkey design teams within the semicon space. They are looking for a number of UVM Verification Engineers to join the team in Canada on a permanent basis.

They can offer hybrid work with some days spent onsite in Ottawa and can even support relocation to Canada so international applicants are encouraged.

Please note - remote work from outside Canada is not available

What will you do?

• Prime the verification activities for a block or an entire chip.
• Document test environment associations and write test cases.
• Employ constrained random verification approaches when possible.
• Support lab bring-up with direct test cases.
• Perform code and functional coverage.

What we look for in return is:

• 10+ years of experience in ASIC verification.
• Highly skilled in Verilog, SystemVerilog, other hardware description languages, and scripting languages.
• Significant experience with OVM/UVM methodologies.
• Familiarity with constrained random verification techniques, assertions, and functional coverage.

Any of the following will be considered a plus:

• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.

If this sounds interesting and you'd like to learn more, click the link below to apply or email me with a copy of your CV on [e-mail]

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Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Engineering, Information Technology, and Other

Industries

Semiconductor Manufacturing, Computer Hardware Manufacturing, and Software Development