Staff Verification Engineer

Synopsys, Inc.; Markham; On-site; CAD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company as a Verification Engineer, where your expertise in UVM and System Verilog will drive innovation in chip design. Collaborate with a dynamic team to enhance the quality of Verification IP and ensure seamless integration of complex protocols. This role offers the opportunity to mentor junior engineers, contribute to cutting-edge methodologies, and play a pivotal role in delivering high-performance solutions. Embrace the chance to make a significant impact while enjoying a comprehensive benefits package that supports your health and wellness.

Benefits

Health benefits

Wellness programs

Financial benefits

Qualifications

• 7-12 years of experience in verification engineering.
• Expertise in UVM and System Verilog.
• Experience in developing reusable verification environments.

Responsibilities

• Contributing to the development of Verification IP with a focus on innovation.
• Leading the design and implementation of verification environments.
• Mentoring junior engineers and promoting best practices.

Skills

UVM

System Verilog

Verification IP modeling

Test case coding

Scoreboard design

Assertions

Checkers

Functional coverage

Problem-solving skills

Job description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned verification engineer with 7 to 12 years of experience in chip design and verification. With a deep understanding of UVM and System Verilog, you excel in verification IP modeling, test case coding, scoreboard design, assertions, checkers, and functional coverage. You have played a driving role in developing reusable verification environments for at least two verification projects using VMM/OVM/UVM methodologies. Your expertise spans multiple protocols, including UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocols. As a detail-oriented and proactive professional, you thrive in collaborative environments and are known for your problem-solving skills and ability to drive technical excellence.

What You’ll Be Doing:

• Contributing to the development of Verification IP (VIP) with a focus on innovation and efficiency.
• Reviewing and signing off on VIP development and updates from both technical and methodological perspectives.
• Collaborating with architects and methodology experts to resolve issues and drive architectural and methodological outputs.
• Serving as the local 'go-to' person for all technical aspects of VIP.
• Leading the design and implementation of verification environments and ensuring their reusability and scalability.
• Mentoring junior engineers and promoting best practices in verification processes.

The Impact You Will Have:

• Enhancing the robustness and reliability of our Verification IP, ensuring top-tier quality and performance.
• Driving innovation in verification methodologies, contributing to the advancement of our technology.
• Ensuring seamless integration and functionality of complex protocols within our products.
• Increasing the efficiency and effectiveness of our verification processes, leading to faster time-to-market.
• Building a culture of technical excellence and continuous improvement within the team.
• Empowering our customers by providing reliable and high-performance verification solutions.

What You’ll Need:

• 7 to 12 years of experience in verification engineering with expertise in UVM and System Verilog.
• Proven experience in verification IP modeling, test case coding, scoreboard design, assertions, checkers, and functional coverage.
• Experience in developing reusable verification environments using VMM/OVM/UVM methodologies.
• In-depth knowledge of protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory protocols.
• Strong problem-solving skills and the ability to drive technical excellence.

Who You Are:

• A proactive and detail-oriented professional who thrives in collaborative environments.
• An excellent communicator who can effectively convey complex technical concepts to diverse audiences.
• A mentor and leader who promotes best practices and continuous learning.
• A strategic thinker who can drive innovation and improvements in verification processes.
• A dedicated team player committed to achieving operational goals and contributing to the company's success.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team of verification engineers dedicated to developing high-quality Verification IP. Our team is focused on advancing verification methodologies and ensuring the seamless integration and functionality of complex protocols. We collaborate closely with architects, methodology experts, and other engineering teams to drive technical excellence and deliver cutting-edge solutions to our customers.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.