ASIC Digital Verification, Sr Staff Engineer

Synopsys, Inc.; Mississauga, Markham, Ottawa; Hybrid; CAD 90,000 - 150,000; Full time

Job summary

An established industry player is seeking a highly motivated Sr Staff Digital Verification Engineer to join their innovative team. This role focuses on verifying cutting-edge SerDes products, requiring a wealth of experience in digital verification and proficiency in SystemVerilog and UVM. You will be responsible for designing testbenches, debugging complex issues, and guiding junior engineers while collaborating with various design groups. The company offers a dynamic work environment that fosters professional growth and continuous technological innovation, ensuring that your contributions significantly impact the development of high-performance silicon solutions.

Benefits

Health Benefits

Wellness Programs

Financial Benefits

Training Opportunities

Qualifications

• 8+ years of digital design/verification experience required.
• Proficient in SystemVerilog and UVM for ASIC verification.

Responsibilities

• Verifying ASIC RTL designs at chip and block levels.
• Designing SystemVerilog testbenches using UVM methodology.
• Debugging RTL and gate-level simulation failures.

Skills

SystemVerilog

UVM

Digital Verification

Problem-Solving

Communication Skills

Debugging

Testcase Writing

Firmware Debug

Education

BSEE

MSEE

Tools

Jira

Python

Perl

Job description

Position: ASIC Digital Verification, Sr Staff

Locations: Mississauga, Markham, Ottawa, Canada Remote

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

We are seeking a highly motivated and innovative Sr Staff digital verification engineer. The ideal candidate is passionate about technology, driven by challenges, and eager to work on cutting-edge SerDes products. You bring a wealth of experience in digital verification, and you are proficient in SystemVerilog/UVM. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to guide junior peers and network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams. You are self-motivated, proactive, and committed to producing high-quality designs while meeting tight deadlines.

What You’ll Be Doing:

• Verifying ASIC RTL designs at both chip and block levels
• Defining and tracking verification testplans
• Designing and writing constrained-random SystemVerilog testbenches using a Verification Methodology such as UVM (Universal Verification Methodology)
• Creating and examining Functional Coverage
• Writing SystemVerilog assertions
• Debugging RTL and gate-level simulation failures
• Firmware Debug
• Bug Tracking using Software Tools such as Jira
• Code Coverage Analysis
• Guiding junior peers and networking with senior personnel within and outside the functional area

The Impact You Will Have:

• Driving the development of high-performance, low-power silicon IP solutions
• Contributing to the advancement of next-generation NRZ and PAM-based SerDes products
• Enabling faster time-to-market for differentiated products with reduced risk
• Improving the functionality and performance of prototype test-chips through rigorous testing
• Supporting the continuous innovation and technological advancement at Synopsys

What You’ll Need:

• BSEE or MSEE with a minimum of 8 years of digital design/verification experience
• Experience in writing testcases in Verilog and SystemVerilog
• Experience in debugging complex testbench and design related issues
• Solid understanding of digital circuit design
• Familiarity with scripting languages (Python or Perl)
• Self-learner, independent, good organization and communication skills

Who You Are:

• Self-motivated and proactive, capable of working independently and as part of a team
• Excellent communication skills for interacting with different design groups and customer support teams
• A problem-solver who resolves issues in clever ways and exercises impartial judgment
• A team player who contributes to the success of the team and guides junior peers

The Team You’ll Be A Part Of:

You will be part of an experienced mixed-signal design and verification team, targeting the next generation NRZ and PAM-based SerDes products. Our team is composed of veteran digital and mixed-signal engineers who are committed to delivering high-end mixed-signal designs from specification development to performing functional and performance tests on prototype test-chips. We foster a collaborative and dynamic environment that provides continuous training and professional growth opportunities.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please [e-mail].