Senior SoC Power & Clocking Architect

Arm; Toronto; Hybrid; CAD 285,000 - 336,000; Full time

Benefits offered by this job

Competitive base salary

Annual bonus

RSUs

401k matching

Excellent PTO

Family bonding time

Competitive benefits

Quarterly days of care

Job summary

Arm seeks a highly skilled SoC Engineering Leader to direct a diverse team delivering Architecture and Verified Designs for Power and Clocking. You will lead a global, multi-functional group responsible for SOC-level clock, reset, power and thermal management architecture to ensure efficient use of system resources.

The role requires 20+ years in SoC architecture and HW design, with strong leadership and experience in DVFS, power gating, and SCMI/ACPI.

Qualifications

• 20+ years of experience in SoC architecture and hardware design.
• Experience architecting, developing and delivering clock, reset, power and thermal solutions.
• Ability to lead a global multi-functional team and external partners.
• Strong ability to synthesize requirements into optimized solutions.

Responsibilities

• Direct a global, multi-functional team delivering SOC clocking, power and thermal architectures.
• Gather requirements, prototype, and implement SOC-level clock, reset and power management.
• Collaborate with partners, OEMs and internal software teams across the development lifecycle.
• Drive on-time, to-specification delivery of complex projects.

Skills

SoC architecture

Power management

Clocking design

Leadership

Cross-functional collaboration

ARM SCMI/PCSA/ACPI knowledge

DVFS and Power Gating

Education

Bachelor’s degree in science or engineering

Master’s Degree preferred

Job description

Arm seeks a highly skilled SoC Engineering Leader to direct a diverse team delivering Architecture and Verified Designs for Power and Clocking. You will lead a global, multi-functional group responsible for SOC-level clock, reset, power and thermal management architecture to ensure efficient use of system resources.

The role requires 20+ years in SoC architecture and HW design, with strong leadership and experience in DVFS, power gating, and SCMI/ACPI.