Senior SoC I/O Performance Architect: Data-Driven Leader

Advanced Micro Devices; Vancouver; Hybrid; CAD 150,000 - 210,000; Full time

Benefits offered by this job

AMD Benefits

Job summary

Advanced Micro Devices in Vancouver is seeking a Principal I/O Performance Architect to define and optimize I/O performance across next-generation SoCs—before silicon and after fabrication. You will shape bandwidth, latency, and QoS targets using modeling and data-driven methods to guide architecture and design decisions.

This role sits at the intersection of architecture, modeling, verification, emulation, firmware/software, and post-silicon analysis, driving performance strategy from concept

Qualifications

• Bachelor's, Master's, or PhD in Electrical/Computer Engineering or related field.
• Experience in high-performance I/O, interconnects, memory — PCIe, CXL, InfiniBand, Ethernet.
• Strong data-driven decision making and ability to frame design questions from models and measurements.

Responsibilities

• Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems.
• Build, extend, and apply performance models to evaluate architectural options.
• Analyze data from models, simulations, emulation, traces, and counters and correlate with RTL/post-silicon results.
• Create reusable workloads and KPI-correlation techniques scalable across teams.
• Partner with cross-functional teams and communicate tradeoffs clearly.
• Develop automation and AI-assisted workflows for data processing and exploration.

Skills

I/O performance

SystemC/TLM

C++

Python

Data-driven analysis

Education

Bachelor's degree

Master's degree

PhD

Tools

PCIe

CXL

UCIe

Job description

Advanced Micro Devices in Vancouver is seeking a Principal I/O Performance Architect to define and optimize I/O performance across next-generation SoCs—before silicon and after fabrication. You will shape bandwidth, latency, and QoS targets using modeling and data-driven methods to guide architecture and design decisions.

This role sits at the intersection of architecture, modeling, verification, emulation, firmware/software, and post-silicon analysis, driving performance strategy from concept