Senior Lead, High-Performance Package Design

Synopsys Inc; Ottawa; On-site; CAD 140,000 - 210,000; Full time

Job summary

Synopsys Inc in Ottawa is seeking a senior package design engineer to lead IP test-chip packaging initiatives. You’ll drive 4–6 test-chip package designs annually from requirements through delivery, collaborating with internal teams, customers, and partners to optimize SI/PI performance.

You’ll apply 3D EM modeling with HFSS, define layer stacks, and guide customers through architecture evaluations, balancing electrical performance with manufacturability and cost. English communication required.

Qualifications

• 10+ years in semiconductor package design or related work.
• Strong knowledge of high-speed interconnect and transmission line behavior.
• Experience building and validating 3D electromagnetic models.
• Excellent English communication; able to explain tradeoffs to customers and teams.

Responsibilities

• Lead 4-6 test-chip package designs per year from requirements through delivery.
• Define package requirements, bump maps and layer stack-up for SI/PI.
• Perform hands-on physical design and layout of advanced package substrates.
• Extract electrical models from substrate designs using 3D EM tools and validate against SI/PI.
• Guide customers through package architecture evaluations and trade-offs.
• Resolve design and integration issues balancing electrical performance, manufacturability, cost.
• Provide regular project updates on progress, risks, and decisions

Skills

Package design expertise

Circuit theory & high-speed intercon.

3D electromagnetic modeling

English communication

Education

Bachelor's degree in Electrical Engineering

Tools

Ansys HFSS

EDA tools

Job description

Synopsys Inc in Ottawa is seeking a senior package design engineer to lead IP test-chip packaging initiatives. You’ll drive 4–6 test-chip package designs annually from requirements through delivery, collaborating with internal teams, customers, and partners to optimize SI/PI performance.

You’ll apply 3D EM modeling with HFSS, define layer stacks, and guide customers through architecture evaluations, balancing electrical performance with manufacturability and cost. English communication required.