Senior High-Speed Analog Layout Lead

Celero Communications, Inc.; Ottawa; On-site; CAD 120,000 - 180,000; Full time

Benefits offered by this job

Foundational role

International team culture

Growth opportunities

Job summary

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout of analog/mixed-signal IP blocks for high‑performance optical communication systems.

You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first‑pass silicon success. You will lead floor planning, layout of ADCs/DACs/PLLs, mentor junior engineers across time zones, and perform LVS, DRC, PERC signoffs.

Qualifications

• 10+ years hands-on analog/mixed-signal layout design in CMOS/FinFET.
• Proven IP/layout macro ownership or full-chip layout leadership.
• Experience with LVS, DRC, PERC, ERC signoffs and layout verification.
• Strong collaboration with international/remote teams.

Responsibilities

• Lead physical layout design of complex analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers for optimal layout trade-offs.
• Mentor junior/layout engineers across multiple time zones.
• Perform and debug LVS, DRC, PERC, ERC and other signoffs.
• Contribute to chip-level planning and power/ground grid design.
• Support automation through scripting and tool customization.

Skills

Analog Layout

Mixed-Signal

FinFET CMOS

IP Layout

Leadership

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celero Communication Inc. is seeking a Principal/Senior Analog Layout Engineer to drive the layout of analog/mixed-signal IP blocks for high‑performance optical communication systems.

You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first‑pass silicon success. You will lead floor planning, layout of ADCs/DACs/PLLs, mentor junior engineers across time zones, and perform LVS, DRC, PERC signoffs.