Senior ASIC Verification Tech Lead — On‑Site in BC

Scaledge Technology; Vancouver; Presencial; CAD 120.000 - 190.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Permanent, full-time employment

Collaborative engineering environment

Professional development opportunities

Descripción de la vacante

Scaledge Technology Ltd. is seeking a Senior ASIC Design Verification Technical Lead to provide technical leadership for ASIC, SoC and subsystem verification projects.

The role involves leading verification activities, coordinating tasks within teams, and developing verification environments and test strategies in collaboration with design and cross-functional engineering teams. The ideal candidate has strong hands-on experience in SystemVerilog, UVM, RTL verification, subsystem verification and

Formación

• Bachelor's degree in Electrical/Electronics/Computer Engineering or related field.
• 7+ years of professional verification experience in ASIC/SoC or semiconductor environments.
• Experience leading verification teams and coordinating tasks.

Responsabilidades

• Lead ASIC/SoC/subsystem verification activities.
• Coordinate verification tasks within teams and with design groups.
• Develop verification environments and test strategies.
• Create and maintain UVM-based verification environments.
• Develop constrained-random and directed test cases to exercise designs.
• Analyze regressions and debug RTL/verification failures.
• Ensure coverage closure and track verification progress.
• Mentor junior engineers and contribute to process improvements.

Conocimientos

SystemVerilog

UVM

RTL verification

subsystem verification

simulation/debugging

technical leadership

team coordination

testbench development

coverage analysis

verifications environments

Educación

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related discipline

Herramientas

Synopsys VCS

Verdi

QuestaSim

ModelSim

Cadence JasperGold

Descripción del empleo

Scaledge Technology Ltd. is seeking a Senior ASIC Design Verification Technical Lead to provide technical leadership for ASIC, SoC and subsystem verification projects.

The role involves leading verification activities, coordinating tasks within teams, and developing verification environments and test strategies in collaboration with design and cross-functional engineering teams. The ideal candidate has strong hands-on experience in SystemVerilog, UVM, RTL verification, subsystem verification and