Senior ASIC Design Verification Engineer

Qualcomm; Toronto; On-site; CAD 80,000 - 120,000; Full time

Job summary

An established industry player in wireless technology is seeking a talented engineer to join their WLAN HW team. In this dynamic role, you will be responsible for verifying and enhancing cutting-edge WLAN/WiFi solutions that set benchmarks in the industry. You will engage in end-to-end design verification tasks, collaborating with global teams to ensure the highest quality deliverables. This position offers an exciting opportunity to work on innovative methodologies and contribute to the development of state-of-the-art wireless technologies. If you have a passion for wireless communications and a strong background in ASIC design and verification, this could be the perfect opportunity for you.

Qualifications

• 2+ years of ASIC design or verification experience required.
• Strong SystemVerilog and UVM skills are essential.

Responsibilities

• Verify PHY Sub-System and ensure high-quality deliverables.
• Develop test plans and validate design components for WiFi standards.

Skills

SystemVerilog

UVM

Debugging Skills

Analytical Skills

Problem-Solving Skills

WiFi Standards Knowledge

Perl

Python

Formal Verification

Education

Bachelor's degree in Science or Engineering

Master's degree in Science or Engineering

PhD in Science or Engineering

Tools

GLS

Scripting Tools

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm WLAN HW team is responsible for the development and delivery of best-in-class WLAN/WiFi solutions that are setting benchmarks in the wireless industry. In this role, you will be verifying our PHY Sub-System and ensuring highest quality deliverables.

Job responsibilities:

• Understanding of WLAN PHY TX and RX design paths
• Verifying algorithms that control the various aspects of wireless systems
• Develop test plans to verify WiFi Standards, creating test sequences, and validating design components
• Own end-to-end DV tasks from coding Test benches, test cases creation, crafting assertions, running simulations, and achieving all coverage goals
• Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches
• Successful candidate will be required to collaborate with worldwide design, silicon, and architecture teams to achieve all project goals

Required Skillset:

• Strong SystemVerilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology
• Strong debugging, Analytical and problem-solving skills
• Experience in formal / static verification methodologies will be a plus
• Good understanding of WiFi or other wireless communications standards is a plus
• Experience with GLS, and scripting languages such as Perl, Python is a plus

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.

Preferred Qualifications:

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 3+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.