Senior Analog Layout Engineer — 3nm/5nm SoCs

leadIC Design Pvt Ltd; Ottawa; On-site; CAD 90,000 - 130,000; Full time

Job summary

leadIC Design Pvt Ltd in Ottawa, Canada is seeking an experienced Analog Layout Engineer to join our on-site team. You will work on advanced SoCs and IPs, delivering full custom layouts for analog and mixed-signal blocks using Cadence Virtuoso on TSMC 3nm/5nm processes.

The role requires 5+ years in analog/mixed-signal layout, strong extraction and PEX skills, and collaboration with circuit designers across multiple corners to meet tight area, power, and performance targets.

Qualifications

• 5+ years of analog/mixed-signal layout experience.
• Hands-on with TSMC 5nm or 3nm processes.
• Proficient in Cadence Virtuoso (XL/GXL).
• Strong knowledge of matching, shielding, parasitics, and best practices.
• Experience with PEX and post-layout collaboration.
• Familiar with Calibre/Assura for DRC, LVS, and physical verification.

Responsibilities

• Execute full custom layout of analog and mixed-signal blocks.
• Participate in floorplanning, placement, routing, and optimization.
• Drive layout closure across multiple PVT corners.
• Ensure DRC, LVS, ERC, and EM/IR compliance.
• Collaborate on LDE, parasitic extraction, and post-layout checks.
• Deliver layouts for TSMC 3nm/5nm with target area, power, and performance.

Skills

Analog/mixed-signal layout

TSMC 3nm/5nm

Cadence Virtuoso XL/GXL

Matching & shielding

Parasitics & LDE

PEX & post-layout

Calibre/Assura

Tools

Cadence Virtuoso

Calibre/Assura

Voltus-Fi

Job description

leadIC Design Pvt Ltd in Ottawa, Canada is seeking an experienced Analog Layout Engineer to join our on-site team. You will work on advanced SoCs and IPs, delivering full custom layouts for analog and mixed-signal blocks using Cadence Virtuoso on TSMC 3nm/5nm processes.

The role requires 5+ years in analog/mixed-signal layout, strong extraction and PEX skills, and collaboration with circuit designers across multiple corners to meet tight area, power, and performance targets.