Senior Analog IC Layout Designer

Teledyne Technologies Inc.; Southwestern Ontario; On-site; CAD 131,000 - 174,000; Full time

Benefits offered by this job

Technically challenging sensor ICs

Cross-disciplinary collaboration

Opportunity to grow analog layout and硅

Stable engineering environment

Job summary

Join Teledyne Technologies Incorporated on a team developing high-performance analog and mixed-signal ICs for CMOS image sensor applications. You will turn transistor-level designs into robust silicon layouts, balancing matching, noise, area, reliability, and manufacturability.

Collaborate with analog designers across schematic to tapeout, tackling layout-dependent performance challenges and contributing to layout reviews while mentoring junior engineers.

Qualifications

• 3+ years of analog/mixed-signal IC layout experience.
• Experience with advanced CMOS technologies and signoff.
• Ability to interpret transistor-level schematics and analog circuit behavior.

Responsibilities

• Create transistor- and block-level layouts for Op-Amps, references, ADC/DACs, PLLs, sensor readout, and high-speed interfaces.
• Optimize floorplans for matching, area, noise isolation, power integrity, and EM reliability.
• Apply layout techniques like common-centroid, interdigitation, symmetry, shielding, guard-ring, and dummy-devices.
• Run and resolve DRC, LVS, ERC, density, and fill verification.
• Minimize parasitic coupling and layout-dependent effects; support parasitic extraction and tapeout.
• Collaborate with design, process, reliability, verification, and CAD teams; mentor junior engineers.

Skills

Analog/mixed-signal IC layout

Transistor-level schematics

3+ years experience

Analog matching & parasitics

Reliability & ESD awareness

Education

Bachelor’s or Master’s in EE/CE/Physics

Tools

Cadence Virtuoso

Calibre

Assura

Job description

Join Teledyne Technologies Incorporated on a team developing high-performance analog and mixed-signal ICs for CMOS image sensor applications. You will turn transistor-level designs into robust silicon layouts, balancing matching, noise, area, reliability, and manufacturability.

Collaborate with analog designers across schematic to tapeout, tackling layout-dependent performance challenges and contributing to layout reviews while mentoring junior engineers.