Senior Analog Layout Engineer

leadIC Design Pvt Ltd; Ottawa; On-site; CAD 90,000 - 150,000; Full time

Job summary

leadIC Design Pvt Ltd in Ottawa, Canada is seeking an experienced Analog Layout Engineer with 5–15 years of hands-on experience in analog and mixed-signal layout for high-performance SoCs. The role focuses on delivering layouts for advanced nodes (TSMC 3nm/5nm) and collaborating with multi-disciplinary teams to optimize performance and area.

You will drive floorplanning, placement, routing, and timing-aware layout, ensure DRC/LVS/EM/IR compliance, and coordinate with circuit designers to address

Qualifications

• 5+ years of analog/mixed-signal layout experience.
• Hands-on with TSMC 3nm/5nm processes.
• Proficient in Cadence Virtuoso.
• Strong understanding of matching, shielding and parasitics.
• Experience with PEX and post-layout simulation.
• Familiar with DRC/LVS/EM/IR verification.

Responsibilities

• Execute full custom layout of analog and mixed-signal blocks.
• Participate in floorplanning, placement, routing, and optimization.
• Drive layout closure across multiple PVT corners.
• Ensure compliance with DRC, LVS, ERC, and EM/IR requirements.
• Collaborate with circuit designers to address LDE and PEX.
• Deliver layout for 3nm/5nm technologies with aggressive area, power, and performance goals.

Skills

Analog/mixed-signal layout

TSMC 3nm/5nm

Cadence Virtuoso

Matching

Parasitics

PEX

DRC/LVS/EM/IR

Tools

Cadence Virtuoso XL/GXL

Calibre/Assura

Voltus-Fi

Python

Tcl

Layout automation

Job description

Position: Analog Layout Engineer
Experience: 5 to 15 Years
Location: Ottawa, Canada
Job Type: Full-Time / Permanent
Work Model: Onsite

Role Overview

We are seeking a skilled Analog Layout Engineer with strong hands-on experience in advanced nodes (TSMC 3nm or 5nm) to join our layout design team in Canada. The ideal candidate will have a solid background in the layout of analog and mixed-signal circuits for high-performance SoCs and IPs.

Key Responsibilities

• Execute full custom layout of analog and mixed-signal blocks (e.g., op-amps, bandgaps, comparators, LDOs, PLLs, data converters)

• Participate in floorplanning, placement, routing, and optimization of analog blocks

• Drive layout closure with designers across multiple PVT corners

• Ensure compliance with DRC, LVS, ERC, and EM/IR requirements

• Collaborate with circuit designers to address layout-dependent effects (LDE), parasitic extraction (PEX), and performance-sensitive layout

• Deliver layout for TSMC 3nm/5nm technologies, meeting aggressive area, power, and performance goals

Required Skills

• 5+ years of experience in analog/mixed-signal layout

• Hands-on experience with TSMC 5nm or 3nm process nodes

• Proficient in using Cadence Virtuoso layout tools (XL/GXL)

• Strong understanding of matching, shielding, parasitics, and analog layout best practices

• Experience with PEX (Parasitic Extraction) and post-layout simulation collaboration

• Familiarity with Calibre/Assura for DRC, LVS, and physical verification

Good to Have

• Experience with EM/IR analysis tools (e.g., Voltus-Fi)

• Scripting skills (Skill, Python, or Tcl)

• Background in layout automation techniques

• Exposure to high-speed layout (SerDes, DDR, PLLs)

Why Join Us

• Opportunity to work on leading-edge 3nm/5nm analog IPs

• Collaborative work environment with exposure to world-class SoC teams

• Competitive compensation and career growth path