Data Accelerator - RTL Design Engineer – Lead

AMD; Markham; On-site; CAD 150,400 - 225,600; Full time

Benefits offered by this job

Comprehensive benefits package

Career development opportunities

Job summary

A leading semiconductor company is seeking an RTL Design Engineer – Lead in Markham, Ontario. This role involves leading a front-end IP design team for custom hardware accelerators aimed at servers and data centers. Ideal candidates will have a Bachelor's or Master’s degree in Computer or Electrical Engineering, with proven experience in ASIC design and IP block development. Strong communication skills are essential, along with a hands-on approach to driving projects forward and mentoring peers. Competitive compensation and comprehensive benefits are included.

Qualifications

• Proven track record of ASIC design on production tape‑outs.
• Experience designing IP blocks for SOC.
• Ability to develop clear and concise engineering documentation.

Responsibilities

• Own major portions of the design and implementation of blocks.
• Collaborate with architecture teams to understand requirements.
• Lead and mentor other design engineers.

Skills

ASIC design

IP block design for SOC

Scripting (PERL, Python, Tcl)

Static timing analysis

Strong communication skills

Education

Bachelor's or Master’s degree in Computer Engineering or Electrical Engineering

Tools

Industry-standard simulation tools

Static analysis tools

Job description

Join to apply for the RTL Design Engineer – Lead role at AMD

Base pay range

$150,400.00/yr - $225,600.00/yr

Seniority Level

Mid‑Senior Level

Employment Type

Full‑time

Role Overview

The Data Accelerator (DACC) team at AMD seeks a Silicon Design Engineer to lead a front‑end IP design team. This role focuses on custom hardware accelerators for servers, data centers, and embedded systems, offering an early career opportunity in a rapidly expanding domain of custom hardware accelerators.

Key Responsibilities

• Own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture teams to understand the requirements.
• Lead and mentor other design engineers to achieve project goals and organizational growth.
• Work with verification, implementation, and physical design teams to achieve high quality design and successful tape‑outs.
• Contribute in cross‑functional teams to solve novel problems across multiple areas in development of required features.
• Support post‑silicon team to ensure successful bring‑up.
• Effectively communicate with multi‑disciplinary teams across the globe.
• Attend and present in status meetings on a weekly/bi‑weekly basis.

Preferred Experience

• Proven track record of ASIC design on production tape‑outs.
• Experience in designing IP blocks for an SOC.
• Experience with industry‑standard simulation and static analysis tools.
• Experience with synthesis, static timing analysis and timing/power optimizations.
• Experience with automation using scripting techniques such as PERL, Python or Tcl.
• Familiarity with using AI for design a plus.
• Ability to develop clear and concise engineering documentation.
• Strong verbal and written communication skills.
• Exhibit strong ownership of tasks and responsibilities.

Academic Credentials

Bachelor's or Master’s (preferred) degree in Computer Engineering or Electrical Engineering.

Location

Markham, Ontario, Canada.

Benefits

Benefits offered are described: AMD benefits at a glance.

Equal Opportunity

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.