Mixed Signal Design Engineer

Net2Source (N2S); Markham; On-site; CAD 96,432 - 103,320; Full time

Job summary

Net2Source (N2S) is seeking an engineer to support pre-silicon integration and post-silicon validation of SERDES PHY IP in Markham, Ontario. The role includes electrical analyses for power, signal, and clock integrity across diverse CLIENT SoC environments, plus collaboration with post-silicon teams for production screening and testing.

The ideal candidate has SERDES or memory PHY design experience and familiarity with jitter, DCD, and clock distribution. Lab validation experience is a plus.

Qualifications

• SERDES PHY IP experience or memory PHY exposure.
• Knowledge of power noise generation and SI basics.
• Experience with lab validation and electrical testing.

Responsibilities

• Support pre-silicon integration and post-silicon validation of SERDES PHY IP.
• Assist electrical analyses for power, signal, and clock integrity across multiple CLIENT SoC environments.
• Support post-silicon teams for production screening, characterization, compliance, and functional testing of 3rd party IP.
• Leverage SERDES or memory PHY design experience and clock/jitter knowledge.

Skills

SERDES PHY IP

Power noise analysis

Signal integrity basics

Clock distribution knowledge

Lab experience with testing/compliance

Memory PHY design experience

Jitter/DCD understanding

Job description

Pay Rate: $(70 to 75)/hr T4

• Support pre-silicon integration and post-silicon support of SERDES PHY IP.
• Support electrical analyses for power, signal, and clock integrity to ensure that SERDES IP operates successfully across many CLIENT SoC environments.
• Support post-silicon teams for production screening, characterization, compliance, and functional testing of 3rd Party IP.
• SERDES or memory PHY design experience of some kind.
• Understanding of power noise generation and sensitivity.
• Understanding of the basics of signal integrity, specifically termination impedance, characteristic impedance, transmission lines.
• Knowledge of clock distribution and clock specifications like jitter, DCD, etc. a plus.
• Some lab experience from functional validation or electrical testing/compliance of SERDES PHYs.