Transmitter (Tx) SerDes Design Engineer — 224G/448G

Ciena; Ottawa; On-site; CAD 138,000 - 220,400; Full time

Job summary

Ciena is seeking a hands-on Transmitter (Tx) SerDes Design Lead in Ottawa to design and deliver high‑speed transmitter macros for 224G/448G SerDes in deep-submicron CMOS. You will own schematic-level design, post-layout verification, and drive simulations across PVT conditions.

Collaborate with system designers, lab validation teams, and layout engineers to ensure architecture aligns with product requirements.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering, or comparable scientific discipline.
• 10+ years of industrial experience designing high-speed analog/mixed-signal/SerDes transmitter circuits in advanced CMOS tech.
• Application of transmitter building blocks including DAC-based output stages, serializers, output drivers, and clocking circuits.
• Post-layout and extraction-based simulations to validate performance across PVT conditions.
• Delivery of analog circuit designs through silicon validation.
• Experience with Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR-RC, MMSIM.

Responsibilities

• Own schematic-level design and post-layout verification of transmitter blocks and DAC-based output stages.
• Collaborate with management, system designers, and lab teams to evolve architecture and meet requirements.
• Evaluate circuit topologies and recommend implementations based on tradeoffs in power, area, and bandwidth.
• Collaborate with layout/design engineers to deliver designs through full GDSII integration.
• Drive extraction-based post-layout simulations and validate performance across PVT conditions.
• Lead root-cause analysis of design and post-layout gaps and implement corrective actions.
• Maintain transmitter performance and power tracking against targets.
• Translate architecture requirements into transmitter implementation; feed learnings back to future designs.
• Build and use behavioral models (Matlab, Verilog-A) to support topology tradeoffs.
• Partner with lab validation to correlate silicon results with simulations and support bring-up.

Skills

High-speed analog design

SerDes transmitter circuits

Schematic design

Post-layout verification

Written and verbal communication

Team collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Cadence

Mentor

Synopsys

Virtuoso

Calibre

STAR-RC

MMSIM

Job description

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Ciena’s WaveLogic family of products enables high-speed optical transmission solutions that are foundational to modern telecommunications networks. This role contributes to the continued advancement of high-speed circuit design for broadband fiber‑optic systems within a vibrant team with a proven track‑record of success over 30 years of evolution in high-speed circuits for broadband fiber‑optic modems — the team that pioneered the world’s first high-speed DAC and ADC analog macros for coherent fiber‑optic products.

We are looking for a hands‑on Transmitter (Tx) SerDes Design Lead to design and deliver our high‑speed electrical transmitter macros for 224G and 448G SerDes in the latest deep‑submicron CMOS technologies.

How You Will Make An Impact

• Own schematic‑level design and post‑layout verification of the transmitter signal chain and its blocks: DAC‑based output stage, serialization, clocking interface, and output driver.
• Work closely with management, system designers, and lab validation teams to evolve the architecture and meet standard and product requirements.
• Evaluate circuit topologies and recommend implementations based on tradeoffs across power, area, bandwidth, and technology constraints.
• Collaborate with layout and design engineers to deliver designs through full GDSII integration.
• Drive extraction‑based post‑layout simulations and validate transmitter performance (bandwidth, linearity/RLM, return loss, jitter, and power) across process, voltage, and temperature conditions.
• Own root‑cause analysis of design‑and post‑layout performance gaps and implement the corrective design actions to meet specifications.
• Maintain block‑ and transmitter‑level performance and power tracking against the agreed targets.
• Translate agreed architecture and system requirements into the transmitter implementation, and feed design and silicon learnings back to inform the next architecture step.
• Build and use behavioral/design models (e.g., MATLAB, Verilog‑A) to support topology tradeoffs and specification alignment.
• Partner with lab validation teams to correlate silicon results with simulations and support test‑chip, product bring‑up and characterization.
• Provide technical guidance and mentorship to more junior design and layout engineers, and report status and share experience with the group on a regular basis.

The Must Haves

• Education: Bachelor’s degree in Electrical Engineering or Computer Engineering, or applicable scientific discipline.
• Experience: 10+ years of industrial experience designing high‑speed analog, mixed‑signal, or SerDes transmitter circuits in advanced CMOS technologies, including schematic design through post‑layout verification.
• Application of transmitter circuit building blocks including DAC‑based output stages, serializers or multiplexers, output drivers, and clocking circuits.
• Execution of post‑layout and extraction‑based simulations to validate performance across process, voltage, and temperature conditions.
• Delivery of analog circuit designs through silicon validation.
• Utilization of Cadence, Mentor, or Synopsys tools including Virtuoso, Calibre, STAR‑RC, and MMSIM.
• Demonstrated written and verbal communication skills and ability to work independently and within a team environment.

Nice To Haves

• Experience: Application of 224G or 448G PAM4 or PAM6 SerDes and related OIF‑CEI or IEEE standards.
• Experience contributing to transmitter architecture using MATLAB, Verilog‑A, or C++.
• Application of signal integrity, power integrity, channel, and package co‑design methodologies, including use of EM tools such as HFSS or EMX.
• Experience mentoring engineers within analog macro design teams.
• Experience with mixed‑signal validation using high‑speed measurement and probing equipment.

Pay Range

The annual salary range for this position is $138,000 - $220,400 CAD. Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.

Non‑Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company‑paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.