Memory Subsystem Verification Engineer

QUALCOMM, Inc.; Vancouver; Presencial; CAD 108.000 - 158.000; Jornada completa

Descripción de la vacante

Qualcomm Canada ULC is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team. The role focuses on developing verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY‑related logic, and high‑performance memory subsystems.

Replacement Position. This role involves full verification lifecycle: plan development, UVM‑based testbenches, assertions, simulations, debugging failures, and

Formación

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 3–10 years of ASIC/SoC/IP design verification experience.
• Hands-on Verilog/SystemVerilog/UVM knowledge and assertions.
• Experience building reusable UVM testbenches and environments.

Responsabilidades

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build and maintain SystemVerilog/UVM environments and formal verification components.
• Create constrained-random, directed, and corner-case tests and write SV assertions.
• Verify memory-controller, PHY interfaces, and memory-subsystem functionality across modes.
• Analyze failures with waveforms, logs, and transaction databases; drive root-cause analysis.
• Collaborate with RTL, architecture, modeling, and validation teams to resolve issues.
• Support regression, triage failures, and report verification status.

Conocimientos

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Educación

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master’s degree in Science, Engineering, or related field (preferred)

PhD (optional)

Herramientas

Formal verification environments

Descripción del empleo

Qualcomm Canada ULC is seeking a motivated and experienced Design Verification Engineer to join its memory subsystem verification team. The role focuses on developing verification strategies for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY‑related logic, and high‑performance memory subsystems.

Replacement Position. This role involves full verification lifecycle: plan development, UVM‑based testbenches, assertions, simulations, debugging failures, and