Memory Subsystem Verification Engineer

Qualcomm; Markham; On-site; CAD 146,000 - 215,000; Full time

Job summary

Qualcomm Canada ULC seeks a Design Verification Engineer to join its memory subsystem verification team. You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic, and drive functional and code coverage closure.

The candidate should have hands-on Verilog, SystemVerilog, UVM and SVA experience, and a strong interest in LPDDR, DDR, and HBM technologies, collaborating with RTL, architecture, and modeling teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
• 3–10 years of experience in ASIC, SoC, IP, or subsystem design verification.
• Strong hands-on experience with Verilog, SystemVerilog, UVM, SystemVerilog Assertions.

Responsibilities

• Develop verification strategies, test plans, and coverage plans for complex RTL designs.
• Build, enhance, and maintain reusable SystemVerilog/UVM and formal verification environments.
• Develop and maintain UVM components: sequences, drivers, monitors, scoreboards, agents, environments, and coverage models.
• Create and execute constrained-random, directed, error-injection, and corner-case tests.
• Write and maintain SystemVerilog Assertions for protocol, interface, timing, and verification.

Skills

Verilog

SystemVerilog

UVM

SystemVerilog Assertions

Constrained random

Debugging

Memory systems

RTL verification

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science

Master’s degree in Science/Engineering (optional)

PhD in Science/Engineering (optional)

Tools

UPF

Waveform viewers

Simulation logs

Job description

Qualcomm Canada ULC seeks a Design Verification Engineer to join its memory subsystem verification team. You will develop verification strategies for memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic, and drive functional and code coverage closure.

The candidate should have hands-on Verilog, SystemVerilog, UVM and SVA experience, and a strong interest in LPDDR, DDR, and HBM technologies, collaborating with RTL, architecture, and modeling teams.