DSP/AI Processor ASIC Design Intern (16m, Markham)

QUALCOMM, Inc.; Markham; On-site; CAD 76,000 - 144,000; Full time

Benefits offered by this job

Housing stipend

Competitive hourly pay

Professional development workshops

Job summary

Qualcomm Canada ULC invites interns for the 2027 AI & Machine Learning Hardware Engineering internships in Markham. You will work under an experienced engineer to design, verify, and model ASIC HW IP for ML end-user applications, learning HDL-based development and verification on real silicon.

Roles cover SystemVerilog, SystemC, C/C++, Python, and UVM, with a focus on multi-phase ASIC development from spec to post-silicon. Housing stipend and competitive pay are part of the internship package.

Qualifications

• Currently enrolled in a bachelor’s or master’s degree program in computer engineering, computer science, electrical engineering, or a related field.
• Strong problem-solving skills and ability to work in a fast-paced team environment.
• Knowledge of ASIC design and verification basics and HDL languages.

Responsibilities

• Implement modules in SystemVerilog and HLS C/C++/SystemC for ASIC HW IP.
• Develop tests at module and subsystem levels using UVM and SystemVerilog.
• Integrate interfaces and build reference models in C++, SystemC, or Python.
• Contribute to design/verification methodology and automation using scripting.
• Assist with timing closure, power analysis, and silicon debugging.

Skills

Digital Logic

Digital Design

Verilog/VHDL

SystemVerilog

SystemC

Python

Teamwork

Education

Bachelor or Master in EE/CS/CE

Tools

SystemVerilog

SystemC

Python

UVM

Synthesis Tools

Job description

Qualcomm Canada ULC invites interns for the 2027 AI & Machine Learning Hardware Engineering internships in Markham. You will work under an experienced engineer to design, verify, and model ASIC HW IP for ML end-user applications, learning HDL-based development and verification on real silicon.

Roles cover SystemVerilog, SystemC, C/C++, Python, and UVM, with a focus on multi-phase ASIC development from spec to post-silicon. Housing stipend and competitive pay are part of the internship package.