RF/Analog Verification Intern – AI-Driven Pre-Silicon

QUALCOMM, Inc.; Markham; On-site; CAD 55,000 - 103,000; Full time

Benefits offered by this job

Housing stipend

Competitive hourly pay

Job summary

Qualcomm Canada ULC is seeking an enthusiastic Interim Engineering Intern - HW to support pre-silicon verification of RFICs for WLAN/BT/UWB and PMU applications in Markham, Canada. You will help develop an AI-driven verification framework to analyze calibration architectures and generate testbench scenarios, enhancing coverage across RF/analog and digital subsystems.

The role involves writing behavioral SystemVerilog models, building verification plans, and debugging tests.

Qualifications

• Enrolled in a bachelor’s, master’s, or PhD in EE, CE, CS or related field.
• Coursework in VLSI digital and RF design.
• Programming experience in C/C++ and Python.

Responsibilities

• Write behavioral SystemVerilog models of analog blocks.
• Develop and maintain functional verification plans and coverages.
• Create functional verification tests for block and radio chip levels.
• Develop and debug event-driven behavioral models for simulation.
• Verify radio chip level functionality and diagnose issues.

Skills

VLSI digital/RF design coursework

Machine learning algorithms

C/C++ programming

Python programming

SystemVerilog

UVM

testbench generation

assertions

functional coverage

stimulus generation

Education

BSEE or BSCS with focus in VLSI digital/RF design

Master’s or PhD candidate in EE, ECE, CE, or CS

Bachelor’s/Master’s/PhD in Electrical/Computer Engineering or CS in progress

Tools

SystemVerilog

UVM

testbench generation

assertions

functional coverage

stimulus generation

Python

C++

TensorFlow

PyTorch

Job description

Qualcomm Canada ULC is seeking an enthusiastic Interim Engineering Intern - HW to support pre-silicon verification of RFICs for WLAN/BT/UWB and PMU applications in Markham, Canada. You will help develop an AI-driven verification framework to analyze calibration architectures and generate testbench scenarios, enhancing coverage across RF/analog and digital subsystems.

The role involves writing behavioral SystemVerilog models, building verification plans, and debugging tests.