Director, AI-Native Silicon & Chip Design (Hybrid)

Octopyd; Toronto; Hybrid; CAD 270,000 - 300,000; Full time

Job summary

Cognichip in Toronto, Canada, is seeking a Director of Silicon Engineering to scale our AI-native chip design organization. This leader will bridge deep technical expertise with strategic management to build a high-performing team capable of shipping production ASIC/SoC products.

Collaborating with Product, SW, and AI teams, you will pioneer AI-first hardware tools and define the technical roadmap to transform chip-design knowledge into actionable workflows.

Qualifications

• 20+ years of experience across architecture, RTL design, verification, and physical design stages.
• Proven experience building and leading engineering teams of 20+.
• Track record of shipping multiple production ASIC/SoC products end-to-end.
• Experience with, and exposure to, AI/ML-driven chip design workflows, tooling.
• Experience with CAD systems; experience integrating workflows with EDA tools.

Responsibilities

• Build, lead, and grow a high-performing hardware engineering team, including hiring, mentoring, and establishing management structure as the org scales
• Set the technical roadmap for translating chip-design expertise into AI-consumable knowledge bases, agent playbooks, model training data, and tool-aware workflows
• Own delivery of production-quality outcomes on schedule, partnering closely with Product, SW and AI/ML teams

Skills

Architecture and RTL design

Verification

Physical design

Leadership of 20+ engineers

AI/ML-driven chip design workflows

Tools

EDA tools

CAD systems

Job description

Cognichip in Toronto, Canada, is seeking a Director of Silicon Engineering to scale our AI-native chip design organization. This leader will bridge deep technical expertise with strategic management to build a high-performing team capable of shipping production ASIC/SoC products.

Collaborating with Product, SW, and AI teams, you will pioneer AI-first hardware tools and define the technical roadmap to transform chip-design knowledge into actionable workflows.