Digital - Digital Design Engineer (title will reflect experience)

Eliyan; Toronto, Vancouver; On-site; CAD 120,000 - 160,000; Full time

Benefits offered by this job

Excellent benefits

Fun work environment

Startup environment

Job summary

A leading technology startup in Toronto is seeking a digital designer to develop cutting-edge chiplet systems. The ideal candidate will have a degree in Electrical Engineering and at least 5 years of high-speed digital design experience, proficient in RTL and SystemVerilog. You will join a dynamic team that values innovation and will work directly on Ethernet designs for high-performance products. This role requires onsite work from Monday to Friday, offering an engaging work environment and excellent benefits.

Qualifications

• 5+ years of experience in high-speed digital design.
• Strong expertise in RTL and Assertion coding with SystemVerilog.
• Proficiency in frontend netlist optimization.
• Knowledge of 100G/200G/400G/800G Ethernet standards.
• Experience integrating 3rd party IPs and startup environments.

Responsibilities

• Design and develop Ethernet PCS/PMA IPs for multiple data rates.
• Collaborate with verification engineers for IP verification.
• Participate in design reviews and ensure design quality.
• Optimize designs for power, area and performance.
• Collaborate with verification and physical design teams.
• Maintain IP design collateral (SDC, UPF/CPF, LINT/CDC) and waivers.
• Stay current with industry trends and standards bodies.

Skills

RTL coding expertise

SystemVerilog proficiency

High-speed digital design

Knowledge of Ethernet standards

Design optimization skills

Education

Bachelors or Masters or Ph.D in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

UPF/CPF

LINT/CDC

RTL synthesis

EDA tools

Job description

Join the leading chiplet startup! As an Eliyan digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architecture specifications and RTL design descriptions for best-in-class PHYs and Controllers. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits. MUST BE WILLING TO WORK ONSITE - M-F

Key Responsibilities

• Design, develop and/or integrate Ethernet PCS/PMA IPs for various data rates (100/200/400/800G)
• Develop micro-architecture specifications and implement digital designs using SystemVerilog
• Ensure compliance with Ethernet standards (IEEE 802.3)
• Optimize designs for power, area, and performance
• Collaborate with verification engineers for IP verification
• Work closely with physical design team for physical implementation
• Participate in design reviews and ensure design quality
• Develop and maintain all IP design collaterals that include documentation, RTL, SDC constraints, power intent definition (UPF/CPF), LINT/CDC rule files and waivers
• Stay up to date with industry trends, emerging technologies and progress in standards’ bodies

Qualifications

• Bachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent
• 5+ years of experience in high-speed digital design (preferably in retimer, gearbox, Ethernet PMA/PCS logic)
• Strong expertise in RTL and Assertion coding with SystemVerilog
• Proficiency in taking RTL through synthesis and produce a PPA optimized frontend netlist
• Knowledge of Ethernet 802.3 standards’ clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link Training
• Strong bias for innovations across all aspects of digital design including automation of mundane activities and methods for quality improvement
• Experience integrating 3rd party mixed signal IPs
• Proven track record of being part of a start-up like environment
• Knowledge of DRAM Controllers/PHYs and HBM Memory a plus