Design Verification Engineer, Senior Staff

Qualcomm; Toronto; On-site; CAD 100,000 - 140,000; Full time

Job summary

Qualcomm Canada ULC is seeking a Senior Staff Design Verification Engineer to lead verification architecture for DSP products, high-speed SerDes, and full-chip SoC verification. You will drive test planning, UVM environments, and pre-silicon validation, collaborating with cross-functional teams to ensure robust product delivery.

The role emphasizes verification closure, production vector signoff, and post-silicon support, with leadership responsibilities and guidance for junior engineers.

Qualifications

• Bachelor’s degree in Science or Engineering with 6+ years ASIC/SoC verification.
• MS with 5+ years or PhD with 4+ years in ASIC verification.
• Expertise with SystemVerilog/UVM and hardware verification methodologies.

Responsibilities

• Architect, develop, and maintain SystemVerilog/UVM verification environments for DSP and SoC.
• Lead verification of DSP functionality, datapaths, and system integration.
• Verify SerDes calibration flows and PMA/PCS interfaces with proper training, equalization, and lane management.
• Own SoC-level verification planning and closure for resets, clocks, and power states.
• Lead ATE functional test development across DSP, SerDes, SoC and signoff.
• Collaborate with Design, DFT, Firmware, Silicon Validation, and ATE teams to transition test content.
• Drive metric-based verification closure across functional coverage, code coverage, and assertions.
• Debug complex multi-clock, multi-power-domain RTL and testbench issues.
• Provide technical leadership and mentor engineers to improve regression efficiency.

Skills

SystemVerilog

UVM

DSP verification

SoC verification

Python scripting

Cross-functional collaboration

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree in related field

PhD in related field

Tools

VCS/Verdi

Xcelium

Questa

Job description

Company:

Qualcomm Canada ULC

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path. Replacement Position

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.ORMaster's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.ORPhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

About the Role

We are seeking a Senior Staff Design Verification Engineer to lead verification architecture and execution for DSP products, high-speed SerDes integration, full-chip SoC verification, and pre-silicon ATE functional test validation. This role will drive verification closure from test planning and UVM environment development through production-oriented ATE vector signoff and post-silicon bring-up support.

What You'll Do

• Architect, develop, and maintain scalable SystemVerilog/UVM verification environments for DSP products, SerDes subsystems, SoC interconnects, and full-chip integration.
• Lead verification of DSP functionality, datapaths, control logic, configuration, performance modes, error handling, and system-level integration.
• Verify SerDes integration, including calibration flows, CDR/PLL control, equalization, lane configuration, deskew, loopback, and digital interface behavior.
• Own SoC-level verification planning and closure for reset/boot flows, clocking, power states, interrupts, CDC/RDC, register access, and high-speed datapaths.
• Lead ATE functional test development across DSP, SerDes, SoC, and related hardware subsystems, including simulation, debug, qualification, and production vector signoff.
• Partner with Design, DFT, Firmware, Silicon Validation, Product Engineering, and ATE teams to transition test content from simulation to silicon and production environments.
• Drive metric-based verification closure across functional coverage, code coverage, assertions, and regression results.
• Debug complex multi-clock, multi-power-domain, RTL, testbench, firmware, and system integration issues.
• Provide technical leadership, mentor engineers, and improve regression efficiency, automation, and debug methodologies.

What You'll Need

• 10+ years of ASIC/SoC design verification experience.
• Strong hands-on expertise with SystemVerilog and UVM, including testbench architecture, sequences, agents, monitors, scoreboards, checkers, and coverage development.
• Experience verifying DSP products, complex SoC subsystems, full-chip integration, and high-speed interfaces.
• Strong understanding of SerDes digital integration, including PMA/PCS interfaces, calibration, training, equalization, clocking, resets, and lane management.
• Experience developing or validating functional test content for ATE, production test, silicon bring-up, or post-silicon validation.
• Proficiency with industry-standard simulation, debug, and coverage tools such as VCS/Verdi, Xcelium, or Questa.
• Strong scripting and automation skills using Python, Perl, Bash, Make, or similar tools.
• Proven ability to lead technical execution across cross-functional and geographically distributed teams.

Preferred Qualifications

• Experience with DSP architectures, signal-processing datapaths, communications products, or high-throughput data processing blocks.
• Knowledge of high-speed protocols such as PCIe, CXL, Ethernet, or custom multi-gigabit PHYs.
• Experience correlating pre-silicon simulation results with post-silicon lab validation or ATE fallout.
• Familiarity with UPF-based power-aware simulation and formal/property verification using SVA or JasperGold.
• Experience improving regression infrastructure, failure triage, and automated debug workflows.

Applicants:

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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