Design Verification Engineer - Senior

LanceSoft, Inc.; Ottawa; On-site; CAD 80,000 - 120,000; Full time

Job summary

A leading technology company is seeking a Design Verification Engineer in Ottawa. This role focuses on functional verification testing, supporting IP development, and requires strong skills in C/C++, UVM, and System Verilog. Applicants should possess a Bachelor's degree and be passionate about modern processor architecture and design verification.

Qualifications

• 5+ years' experience in verification design.
• Good scripting knowledge in Perl, Ruby, and Makefile.
• Familiarity with AXI protocol and Bootcode Verification.

Responsibilities

• Develop and maintain UVM tests for functional verification.
• Build testbench components for next-generation IP.
• Provide technical support to other teams.

Skills

C

C++

UVM

System Verilog

Analytical skills

Problem solving

Teamwork

Communication

Education

Bachelor's degree in computer engineering / Electrical Engineering

Tools

Perl

Ruby

Makefile

Job description

Top priority skills : UVM , system Verilog , C and C++

THE ROLE :

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve abilities to deliver the highest quality, industry-leading technologies to market. The Verification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON :

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites / time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES :

• Develop / Maintain tests for functional verification with UVM verification at the subsystem level
• Build testbench components to support the next generation IP
• Maintain or improve current test libraries to support IP level testing
• Technically lead IPs in Control Fabric,
• Have exposure to AXI protocol and Bootcode Verification
• Provide technical support to other teams

PREFERRED EXPERIENCE :

• 5+ years' experience required
• Good at C / C++
• Good at SV and UVM
• Good scripting knowledge in Perl, Ruby and Makefile
• Familiarity with System Verilog and modern verification libraries like UVM

ACADEMIC CREDENTIALS :

• Bachelors (required) or Masters degree in computer engineering / Electrical Engineering

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Design Verification Engineer • Ottawa, ON, Canada