Digital Design Verification Internship (16-Month Co-op)

Synopsys Inc; Mississauga; Hybrid; CAD 28,000 - 33,000; Full time

Job summary

Synopsys Inc in Mississauga invites a highly motivated engineering student to join our IP Group for a 16-month co-op focused on Digital Design Verification. You will verify Backplane Ethernet, PCIe Gen4/5/6, USB3/4, and MPHYv5/6 SERDES across mixed-signal designs with global teams.

Work will be hybrid, with in-office collaboration and remote work. Start date May 2027; the role provides hands-on experience with verification methodologies (UVM) and opportunities to learn AI-assisted verification

Qualifications

• Pursuing a Bachelor's degree in a relevant engineering field.
• Fundamental knowledge of digital design and verification concepts.
• Familiarity with Verilog or SystemVerilog is required.
• Experience scripting in Perl, shell, or Python is preferred.
• Experience with object‑oriented programming is a plus.

Responsibilities

• Define and track Verification Testplans for design functionality.
• Design and write constrained-random SystemVerilog testbenches (UVM).
• Write SystemVerilog assertions and debug RTL/gate-level sim results.
• Conduct functional and code coverage analyses to improve verification.
• Explore AI-assisted verification applications in ASIC design.

Skills

Digital logic fundamentals

Independence mindset

Willingness to learn

Strong debugging

Education

Bachelor's degree in Computer or Electrical Engineering (in progress)

Related discipline

Tools

Verilog

SystemVerilog

Perl

Unix shell

Python

C++

Java

Job description

We Are

We drive technology innovations that shape the way we live and connect. Our technology powers the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world.

Internship Experience

At Synopsys, interns dive into real-world projects, gaining hands‑on experience while collaborating with our passionate teams worldwide—and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting‑edge technology that shapes not only the future of innovation but also your own career path. Join us and start shaping your future today!

Mission Statement

Our mission is to fuel today's innovations and spark tomorrow's creativity. Together, we embrace a growth mindset, empower one another, and collaborate to achieve our shared goals. Every day, we live by our values of Integrity, Excellence, Leadership, and Passion, fostering an inclusive culture where everyone can thrive - both at work and beyond.

About This Role

We are seeking a highly motivated engineering student willing to learn Digital Design Verification, which is a critical step of the product development process. Design Verification aims to confirm that the design complies with Protocol Standards and System Requirements before it is developed into a chip. Exhaustively verifying functionality in the design phase allows engineers to catch bugs early in the development cycle where they are cheaper and easier to fix.

As part of our IP Group in Mississauga, you'll be involved in verifying current and next-generation Backplane Ethernet, PCIe Gen4/5/6, USB3/4, and MPHYv5/6 SERDES products. This position offers an excellent opportunity to work with digital and mixed-signal design engineers accountable for delivering high-end mixed-signal designs while collaborating with global teams.

What You'll Be Doing

• Define and track Verification Testplans to ensure comprehensive coverage of design functionality
• Design and write constrained-random SystemVerilog testbenches using Verification Methodologies such as UVM (Universal Verification Methodology)
• Write SystemVerilog assertions and debug RTL and gate-level simulation failures
• Conduct functional and code coverage analysis to identify gaps and improve verification quality
• Explore cutting-edge applications and uses of AI-assisted technologies in verification and ASIC design, contributing to innovation in the field

What You'll Need

• Currently pursuing a Bachelor's degree in Computer Engineering, Electrical Engineering, or a related discipline
• Strong understanding of digital logic fundamentals
• Must be familiarity with Verilog and SystemVerilog
• Experience writing scripts in languages such as Perl, Unix shell, or Python
• Experience with object-oriented programming languages (C++, Java, Python, etc.)
• Independence and ownership mindset – you'll need to figure things out on your own at times and take responsibility for your work
• The willingness to learn and grow

Key Program Facts

• Program Length: 16-month co-op internship
• Location: Mississauga, Ontario, Canada
• Working Model: Hybrid (combination of remote work and in-office collaboration at our Mississauga office)
• Full-Time/Part-Time: Full-time (40 hours per week)
• Start Date: May 2027

Equal Opportunity Statement

Synopsys is committed to creating an inclusive workplace and is an equal opportunity employer. We welcome all qualified applicants to apply, regardless of age, color, family or medical leave, gender identity or expression, marital status, disability, race and ethnicity, religion, sexual orientation, or any other characteristic protected by local laws. If you need assistance or a reasonable accommodation during the application process, please reach out to us.