Analog & Mixed Signal Engineer

Sphere Semi; Headquarters; On-site; CAD 110,000 - 170,000; Full time

Job summary

Sphere Semi is seeking an Analog & Mixed Signal Engineer to guide analog/RFIC design from concept to production. You will define verification strategies, key design variables, and test benches for AI-driven design automation while ensuring clean integration with digital blocks.

You may directly create and verify designs, or set up new flows, collaborating across AI teams and customers to accommodate multiple process technologies.

Qualifications

• Ph.D. or Master’s in Electrical Engineering with analog/mixed-signal/RFIC focus.
• Recent graduates or seasoned engineers with tape-out experience encouraged.
• Experience integrating digital and analog components in mixed-signal chips.

Responsibilities

• Define design and verification process to minimize tape-outs.
• Establish design parameters and test benches for AI-driven flows.
• Oversee integration of analog, digital, and RF components.
• Adapt to new tools and evolving internal frameworks.
• Collaborate with AI engineers, software teams and customers.
• Hands-on design and verification as needed.

Skills

Analog design

Mixed-signal design

RFIC design

Design verification

Digital integration

Education

Ph.D. or Master's in Electrical Engineering

Tools

Cadence

Keysight

EDA tools

Job description

Sphere Semi is a new type of semiconductor company, where an AI model designs chips alongside humans. Our AI chip design algorithm allows us to produce customized and optimized designs at scale.

We are seeking an Analog & Mixed Signal Engineer to help ensure the success of our designs, from concept through to production, with a focus on thorough verification and design integration.

Key Responsibilities:

• Define the design and verification process: You will be responsible for ensuring that our approach produces functional chips with a minimal number of tape-outs. In some cases, we are exploring what it will take to achieve first-pass success.
• Define critical design parameters: Establish key design variables, constraints, and test benches that will guide our AI-driven design automation system. Your goal will be to ensure that the system generates meaningful, manufacturable results, while filtering outputs through human review as needed.
• Oversee integration of digital components: As our chip designs may include a mix of analog and digital elements, you will be responsible for ensuring the smooth integration of these components into full chip designs.
• Adapt to and implement new tools: You will be familiar with standard EDA analog and RF toolsets (Cadence, Keysight, etc.), but also be expected to adapt to and work with new and evolving internal tools and frameworks.
• Cross-functional collaboration: Partner with AI engineers, software developers, and chip designers to ensure our automated tools produce optimized designs that can be efficiently taped out. You’ll also work closely with customers and adapt to various process technologies and project needs.
• Hands-on design & verification: In the early stages, you may directly create and validate designs, or set up new design flows. You’ll actively participate in hands-on engineering tasks, ensuring designs are verified before production.

Qualifications:

• Ph.D. or Master’s in Electrical Engineering, with a focus on analog/mixed-signal/RFIC design, or equivalent industry experience.
• Flexibility in experience level: Recent Ph.D. graduates with strong foundational skills and adaptability, or experienced industry veterans with a proven track record, are encouraged to apply.
• Track record of successful tape-outs: Demonstrated experience participating in design teams or projects that resulted in functional analog/RFIC chips in production.
• Experience with digital integration: Familiarity with mixed signal chips that involve close integration between digital and analog components.
• Tool flexibility: Strong knowledge of industry-standard tools, with the ability to adapt to new methodologies and tools beyond traditional EDA.