AI-Driven Chip Verification Engineer

Arcadia; Toronto; Hybrid; CAD 150,000 - 200,000; Full time

Job summary

A well-funded AI and semiconductor startup is seeking a Junior/Intermediate Design Verification Engineer in Toronto, offering a competitive salary of CA$150K to CA$200K plus equity. Responsibilities include writing SystemVerilog/UVM testbenches, defining verification plans, and automating test execution. Ideal candidates should have 1-5 years of experience, familiarity with verification methodologies, and strong scripting skills. The role offers mentorship from senior engineers and the chance to work in a dynamic hybrid environment.

Qualifications

• 1-5 years in ASIC/FPGA verification or chip design internships/projects.
• Familiarity with SystemVerilog, UVM, or similar verification methodologies.
• Strong scripting skills for automation.

Responsibilities

• Write and run SystemVerilog/UVM testbenches to validate RTL blocks.
• Develop directed and constrained-random tests for functional coverage.
• Work with senior engineers to define verification plans.

Skills

SystemVerilog/UVM

Python

TCL

Shell scripting

Digital design fundamentals

AI/ML in chip design

Tools

VCS

Questa

Xcelium

CocoTB

Verilator

Job description

A well-funded AI and semiconductor startup is seeking a Junior/Intermediate Design Verification Engineer in Toronto, offering a competitive salary of CA$150K to CA$200K plus equity. Responsibilities include writing SystemVerilog/UVM testbenches, defining verification plans, and automating test execution. Ideal candidates should have 1-5 years of experience, familiarity with verification methodologies, and strong scripting skills. The role offers mentorship from senior engineers and the chance to work in a dynamic hybrid environment.