Sr. Design Verification Engineer

Arcadia; Toronto; Hybrid; CAD 150,000 - 200,000; Full time

Job summary

A well-funded AI and semiconductor startup is seeking a Junior/Intermediate Design Verification Engineer in Toronto, offering a competitive salary of CA$150K to CA$200K plus equity. Responsibilities include writing SystemVerilog/UVM testbenches, defining verification plans, and automating test execution. Ideal candidates should have 1-5 years of experience, familiarity with verification methodologies, and strong scripting skills. The role offers mentorship from senior engineers and the chance to work in a dynamic hybrid environment.

Qualifications

• 1-5 years in ASIC/FPGA verification or chip design internships/projects.
• Familiarity with SystemVerilog, UVM, or similar verification methodologies.
• Strong scripting skills for automation.

Responsibilities

• Write and run SystemVerilog/UVM testbenches to validate RTL blocks.
• Develop directed and constrained-random tests for functional coverage.
• Work with senior engineers to define verification plans.

Skills

SystemVerilog/UVM

Python

TCL

Shell scripting

Digital design fundamentals

AI/ML in chip design

Tools

VCS

Questa

Xcelium

CocoTB

Verilator

Job description

2 days ago Be among the first 25 applicants

This range is provided by Arcadia. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

CA$150,000.00/yr - CA$200,000.00/yr

Location: Hybrid – Downtown Toronto (4 days/week in office, near Union Station)

Type: Full-time | Permanent

Compensation: $150K–$200K CAD base + early-stage equity

A well-funded AI + semiconductor startup ($30M+ raised) is hiring a junior/intermediate Design Verification Engineer to help reinvent chip verification through AI-native tooling and intelligent automation.

This is a rare chance to get in early, work alongside senior silicon engineers and ML researchers, and build your career on greenfield verification flows that combine traditional SystemVerilog/UVM with cutting-edge AI-driven design tools.

What You’ll Do

• Write and run SystemVerilog/UVM testbenches to validate RTL blocks.
• Develop directed and constrained-random tests for functional coverage.
• Work with senior DV/RTL engineers to define verification plans and metrics.
• Automate test execution, regressions, and coverage collection with Python/scripting.
• Contribute to experiments in AI-assisted verification workflows.

What We’re Looking For

• 1–5 years in ASIC/FPGA verification or chip design internships/projects.
• Familiarity with SystemVerilog, UVM, or similar verification methodologies.
• Strong scripting skills (Python, TCL, or Shell) for automation.
• Solid fundamentals in digital design, RTL, and computer architecture.
• Eager to learn and thrive in a fast-paced startup with strong mentorship.
• Hands-on coursework or internships with EDA tools (VCS, Questa, Xcelium, etc.).
• Exposure to open-source verification frameworks (CocoTB, Verilator).
• Knowledge of on-chip protocols (AXI, SPI, PCIe, DDR).
• Coursework or curiosity around AI/ML in chip design.

Jumpstart your career in AI-powered chip verification

Competitive salary + meaningful equity in a well-funded, deeply technical startup

Learn directly from senior silicon + AI engineers pushing the frontier

Hybrid role in Toronto — high-trust, low-ego team, chance to grow fast